公开(公告)号：US07384496B2

公开(公告)日：2008-06-10

申请号：US10996786

申请日：2004-11-24

Applicant: Andre Cote ,  Eric Eckstein ,  Thomas J. Clare

Inventor： Andre Cote ,  Eric Eckstein ,  Thomas J. Clare

IPC: B32B37/12 ,  B32B38/10 ,  B32B38/14 ,  G08B13/14

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.

Abstract translation: 制造标签的方法包括以下步骤：将第一图案化的粘合剂施加到基底的表面，并将第一导电箔施加到第一图案化的粘合剂上。 去除不粘附到第一图案化的粘合剂的第一导电箔的一部分，并且将第二图案化的粘合剂施加到标签的表面区域的一部分。 将预制的第二导电箔施加到第二图案化的粘合剂以将第二导电箔粘附到基板的表面，并且第一和第二导电箔的部分彼此电耦合以形成标签电路。 第二图案化粘合剂可以设置在第一和第二导电箔之间。

公开(公告)号：US20100218899A1

公开(公告)日：2010-09-02

申请号：US12759400

申请日：2010-04-13

Applicant: Thomas J. Clare ,  Andre Cote ,  Eric Eckstein

Inventor： Thomas J. Clare ,  Andre Cote ,  Eric Eckstein

IPC: B32B41/00 ,  B32B37/00 ,  B23K37/04 ,  B29C65/00

CPC classification number: H01L24/81 ,  B23K20/004 ,  B23K2101/32 ,  B23K2101/40 ,  G06K19/07718 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67132 ,  H01L23/49855 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/75 ,  H01L2224/78 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  Y10T156/12 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A method and apparatus for bonding integrated circuits uniquely suited to high volume tag production is described, where conductive material of a substrate at the die-attach-area is cut before an IC chip or transponder is placed on the conductive material over the cut and bonded. The apparatus performs the method of placing a first chip on a substrate having a conductive layer, measuring the location of the first chip on the substrate, cutting the conductive layer at a location of an expected subsequently placed chip to form a cut based on the measured location of the first chip, and placing the subsequently placed chip on the substrate over the cut.

Abstract translation: 描述了用于接合独特地适用于大容量标签制造的集成电路的方法和装置，其中在芯片附着区域之前的基板的导电材料在将IC芯片或应答器放置在切割和粘合的导电材料之前被切割 。 该装置执行将第一芯片放置在具有导电层的基板上的方法，测量基板上的第一芯片的位置，在预期的随后放置的芯片的位置处切割导电层，以基于测量的 第一芯片的位置，并将随后放置的芯片放置在切口上的基板上。

公开(公告)号：US07709294B2

公开(公告)日：2010-05-04

申请号：US11166534

申请日：2005-06-24

Applicant: Thomas J. Clare ,  Andre Cote ,  Eric Eckstein

Inventor： Thomas J. Clare ,  Andre Cote ,  Eric Eckstein

IPC: H01L21/00 ,  B23K20/00

CPC classification number: H01L24/81 ,  B23K20/004 ,  B23K2101/32 ,  B23K2101/40 ,  G06K19/07718 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67132 ,  H01L23/49855 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/75 ,  H01L2224/78 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  Y10T156/12 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A method and apparatus for bonding integrated circuits uniquely suited to high volume tag production is described, where conductive material of a substrate at the die-attach-area is cut before an IC chip or transponder is placed on the conductive material over the cut and bonded. The apparatus performs the method of placing a first chip on a substrate having a conductive layer, measuring the location of the first chip on the substrate, cutting the conductive layer at a location of an expected subsequently placed chip to form a cut based on the measured location of the first chip, and placing the subsequently placed chip on the substrate over the cut.

Abstract translation: 描述了用于接合独特地适用于大容量标签制造的集成电路的方法和装置，其中在芯片附着区域之前的基板的导电材料在将IC芯片或应答器放置在切割和粘合的导电材料之前被切割 。 该装置执行将第一芯片放置在具有导电层的基板上的方法，测量基板上的第一芯片的位置，在预期的随后放置的芯片的位置处切割导电层，以基于测量的 第一芯片的位置，并将随后放置的芯片放置在切口上的基板上。

公开(公告)号：US07042413B2

公开(公告)日：2006-05-09

申请号：US10914432

申请日：2004-08-09

Applicant: Gary T. Mazoki ,  Anthony F. Piccoli ,  Thomas J. Clare ,  Eric Eckstein

Inventor： Gary T. Mazoki ,  Anthony F. Piccoli ,  Thomas J. Clare ,  Eric Eckstein

IPC: H01Q9/28

CPC classification number: H01Q1/2225 ,  G06K19/07786 ,  H01Q1/22 ,  H01Q9/16 ,  H01Q9/285 ,  H01Q21/24 ,  H01Q21/26

Abstract: A three-dimensional dipole antenna system for an RFID tag that optimizes detection for a given available volume in which to situate the RFID tag.

Abstract translation: 一种用于RFID标签的三维偶极天线系统，其优化针对其中定位RFID标签的给定可用体积的检测。

公开(公告)号：US07119685B2

公开(公告)日：2006-10-10

申请号：US10998496

申请日：2004-11-29

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: G08B13/14

CPC classification number: H01G4/005 ,  G01V15/00 ,  G06K19/07718 ,  G06K19/07786 ,  H01G13/00 ,  H01Q1/38 ,  H01Q9/265 ,  H01Q9/285 ,  H05K1/162 ,  H05K3/041 ,  Y10T29/49117 ,  Y10T29/49133 ,  Y10T29/49155

Abstract: A circuit element the presence of the circuit element includes first and second capacitor plates disposed over the surface of the substrate in an aligned relationship with each other. The aligned relationship has manufacturing variations in the relative positioning of the first and second capacitor plates and a dielectric layer disposed between the first and second capacitor plates. At least one of the first and second capacitor plates is formed substantially smaller relative to the other of the first and second capacitor plates. The at least one of the capacitor plates is disposed at a predetermined offset in at least one planar direction from an edge of the other of the first and second capacitor plates. The predetermined offset is selected according to the manufacturing variations to prevent variations in the value of capacitance of the capacitor due to the manufacturing variations.

Abstract translation: 电路元件的存在包括以彼此对准的关系设置在衬底的表面上的第一和第二电容器板。 对准关系在第一和第二电容器板的相对定位以及设置在第一和第二电容器板之间的电介质层的制造变化。 第一和第二电容器板中的至少一个形成为相对于第一和第二电容器板中的另一个基本上较小。 所述电容器板中的至少一个在与所述第一和第二电容器板的另一个的边缘的至少一个平面方向上以预定的偏移位置配置。 根据制造变化来选择预定的偏移量，以防止由于制造变化而导致的电容器的电容值的变化。

公开(公告)号：US07116227B2

公开(公告)日：2006-10-03

申请号：US10996785

申请日：2004-11-24

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: G08B13/14

CPC classification number: G08B13/2437 ,  G08B13/244 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A tag having a substrate having a surface with a preformed first patterned adhesive disposed over the surface thereof and a first layer of electrically conductive material having a shape corresponding to a desired final pattern for a first electrically conductive trace secured to the surface of the substrate. The preformed first patterned adhesive corresponds to the desired final pattern. A second patterned adhesive is disposed over a portion of a surface area of the tag. An electrically conductive trace is disposed over the second patterned adhesive to adhere the second electrically conductive trace thereto. An electrical connection is provided for electrically coupling portions of the first and second electrically conductive traces to form a tag circuit. The tag circuit can be an LC resonant circuit. The preformed first patterned adhesive can be a flexographic printed layer.

Abstract translation: 一种具有基底的标签，其具有设置在其表面上的预先形成的第一图案化粘合剂的表面，以及第一层导电材料，其具有对应于固定到基底表面的第一导电迹线的期望最终图案的形状。 预成型的第一图案化的粘合剂对应于所需的最终图案。 第二图案化粘合剂设置在标签的表面区域的一部分上。 导电迹线设置在第二图案化的粘合剂上以将第二导电迹线粘附到其上。 提供电连接以电耦合第一和第二导电迹线的部分以形成标签电路。 标签电路可以是LC谐振电路。 预成型的第一图案化胶粘剂可以是柔性版印刷层。

公开(公告)号：US07856708B2

公开(公告)日：2010-12-28

申请号：US11532715

申请日：2006-09-18

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: H05K3/02

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A process for forming a portion of a package or envelope bearing printed indicia, a label bearing printed indicia or a sheet bearing printed indicia includes providing a substrate which constitutes a portion of the package, label or sheet to a printing apparatus, and utilizing the printing apparatus or an adjunct to the printing apparatus to form at least one electrically conductive component of an EAS and/or RFID tag on the substrate substantially contemporaneously with the printing of the indicia on the substrate. The forming of the electrically conductive component on the substrate is accomplished slightly prior to the printing of the indicia on the substrate, slightly after the printing of the indicia on the substrate and at the same time as the printing of the indicia on the substrate.

Abstract translation: 用于形成承载印刷标记的包装或信封的一部分的方法，带有印刷标签的印刷标签或承载印刷标记的片材的方法包括将构成包装，标签或片材的一部分的基材提供到印刷装置，并且利用印刷 装置或辅助装置，以基本上同时在基板上印刷标记而在基板上形成EAS和/或RFID标签的至少一个导电部件。 导电组件在衬底上的形成在印刷衬底上的标记之前略微地完成，稍后在衬底上印刷标记之后，并且与衬底上的标记的印刷同时进行。

公开(公告)号：US07368033B2

公开(公告)日：2008-05-06

申请号：US11399551

申请日：2006-04-06

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: B32B37/12 ,  B32B38/04 ,  B32B38/14 ,  G06K19/02

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.

Abstract translation: 制造标签的方法包括以下步骤：将第一图案化的粘合剂施加到基底的表面，并将第一导电箔施加到第一图案化的粘合剂上。 去除不粘附到第一图案化的粘合剂的第一导电箔的一部分，并且将第二图案化的粘合剂施加到标签的表面区域的一部分。 将预制的第二导电箔施加到第二图案化的粘合剂以将第二导电箔粘附到基板的表面，并且第一和第二导电箔的部分彼此电耦合以形成标签电路。 第二图案化粘合剂可以设置在第一和第二导电箔之间。

公开(公告)号：US20060175003A1

公开(公告)日：2006-08-10

申请号：US11399551

申请日：2006-04-06

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: B32B38/04 ,  B32B38/14 ,  B32B38/10

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.

Abstract translation: 制造标签的方法包括以下步骤：将第一图案化的粘合剂施加到基底的表面，并将第一导电箔施加到第一图案化的粘合剂上。 去除不粘附到第一图案化的粘合剂的第一导电箔的一部分，并且将第二图案化的粘合剂施加到标签的表面区域的一部分。 将预制的第二导电箔施加到第二图案化的粘合剂以将第二导电箔粘附到基板的表面，并且第一和第二导电箔的部分彼此电耦合以形成标签电路。 第二图案化粘合剂可以设置在第一和第二导电箔之间。

公开(公告)号：US20050183817A1

公开(公告)日：2005-08-25

申请号：US10996786

申请日：2004-11-24

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: B44C1/165 ,  G08B13/24 ,  H05K1/16 ,  H05K3/04 ,  B32B31/00

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.

Abstract translation: 制造标签的方法包括以下步骤：将第一图案化的粘合剂施加到基底的表面，并将第一导电箔施加到第一图案化的粘合剂上。 去除不粘附到第一图案化的粘合剂的第一导电箔的一部分，并且将第二图案化的粘合剂施加到标签的表面区域的一部分。 将预制的第二导电箔施加到第二图案化的粘合剂以将第二导电箔粘附到基板的表面，并且第一和第二导电箔的部分彼此电耦合以形成标签电路。 第二图案化粘合剂可以设置在第一和第二导电箔之间。