-
公开(公告)号：US20180301344A1
公开(公告)日：2018-10-18
申请号：US15986304
申请日：2018-05-22
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Samuel Washington , Shailendra Srivastava , Terry Koker , Julianne Lee , Catherine Britt Carlson
IPC: H01L21/306 , H01L31/0236 , C25F3/14 , H01L31/0232 , H01L21/66 , G01B11/24
CPC classification number: H01L21/30604 , B81C1/00103 , B81C1/00111 , B81C1/00119 , B81C1/00214 , B81C1/00484 , B81C1/00539 , B81C1/00595 , B81C2201/0114 , B81C2201/0139 , B81C2201/0157 , C25F3/12 , C25F3/14 , G01B11/2441 , H01L21/30617 , H01L21/3063 , H01L21/76886 , H01L22/12 , H01L31/02327 , H01L31/02363
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
-
Patent Agency Ranking
公开(公告)号：US11038321B2
公开(公告)日：2021-06-15
申请号：US16600030
申请日：2019-10-11
Inventor： Milton Feng , Xin Yu
Abstract: Vertical-cavity surface-emitting lasers (VCSELs) and methods for making such are provided. The VCSELs include stepped upper reflectors having respective differently-sized apertures. This allows the lower portion of the reflector to have formed therein a wider-diameter aperture to allow for increased current injection. The upper portion of the reflector has formed therein a narrower-diameter, mode-selecting aperture to allow higher-order modes to be reduced, leading to single-mode operation. The VCSELs are thus capable of higher-power emission in a single mode, allowing for longer-distance signaling over optical fiber, despite modal dispersion within the fiber and/or at the coupling between the VCSEL and the fiber. The two differently-sized apertures can be formed via respective lateral oxidation processes following etch-down to form the respective steps of the upper reflector. Differences in composition across the upper reflector results in temperature-dependence of the oxidation process, allowing the apertures to be formed with different sizes.
-
3.发明申请公开(公告)号：US20160118265A1
公开(公告)日：2016-04-28
申请号：US14988895
申请日：2016-01-06
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Samuel Washington , Shailendra Srivastava , Terry Koker , Julianne Lee , Catherine Britt Carlson
IPC: H01L21/306 , H01L31/0236 , H01L21/768 , H01L31/0232
CPC classification number: H01L21/30604 , B81C1/00103 , B81C1/00111 , B81C1/00119 , B81C1/00214 , B81C1/00484 , B81C1/00539 , B81C1/00595 , B81C2201/0114 , B81C2201/0139 , B81C2201/0157 , C25F3/12 , C25F3/14 , G01B11/2441 , H01L21/30617 , H01L21/3063 , H01L21/76886 , H01L22/12 , H01L31/02327 , H01L31/02363
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.
Abstract translation: 用于相对于衬底的表面相对地制造三维结构并用于在表面上相加地沉积金属和掺杂剂原子并将其扩散到本体中的方法和装置。 将化学溶液施加到半导体衬底的表面，并且通过将在特定强度，波长和持续时间上的特定的照明的空间图案投影在多个像素的每个像素上来产生电子 - 空穴对的空间图案 表面。 相对于照明的空间模式的时间分布，电势跨越半导体和解决方案的界面以特定的时间分布被施加。 这种方法适用于与抛物面反射器，单元尺寸分选芯片，三维光子带隙芯片，光子集成电路和集成光子微流体电路集成的光电检测器的制造。
-
公开(公告)号：US10115599B2
公开(公告)日：2018-10-30
申请号：US14988895
申请日：2016-01-06
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Terry Koker
IPC: H01L21/306 , C25F3/14 , H01L21/3063 , C25F3/12 , G01B11/24 , H01L21/768 , H01L31/0236 , H01L31/0232 , H01L21/66 , B81C1/00
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.
-
5.发明授权Rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) 有权用于射频集成电路（RFIC）的卷绕电感器结构公开(公告)号：US09224532B2
公开(公告)日：2015-12-29
申请号：US14051188
申请日：2013-10-10
Inventor： Xiuling Li , Wen Huang , Placid M. Ferreira , Xin Yu
IPC: H01F5/00 , H01F27/28 , H01F5/02 , H01F41/02 , H01L49/02 , H01F41/06 , H01L23/64 , H01L21/48 , H01L23/66 , H01F17/00 , H01F41/04 , H01L23/522
CPC classification number: H01F27/2804 , H01F5/00 , H01F5/02 , H01F17/0013 , H01F27/2847 , H01F41/02 , H01F41/041 , H01F2017/006 , H01F2027/2809 , H01F2027/2857 , H01L21/4814 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L28/10 , H01L2223/6627 , H01L2223/6677 , H01L2924/0002 , Y10T29/49071 , H01L2924/00
Abstract: A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure.
Abstract translation: 用于射频集成电路（RFIC）的卷绕电感器结构包括卷绕构型的多层片材，其包围围绕纵向轴线的多个匝数。 多层片材包括在应变消除层上的导电图案层，并且导电图案层包括至少一个沿轧制方向延伸的长度的导电条。 因此，至少一个导电带在卷绕构型中绕纵向轴线缠绕。 导电图案层还可以包括连接到导电条的两个导电馈电线，用于使电流通过。 导电条用作卷起的电感器结构的电感单元。
-
公开(公告)号：US10734237B2
公开(公告)日：2020-08-04
申请号：US15986304
申请日：2018-05-22
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Samuel Washington , Shailendra Srivastava , Terry Koker , Julianne Lee , Catherine Britt Carlson
IPC: H01L21/306 , H01L31/0232 , H01L31/0236 , H01L21/768 , H01L21/3063 , C25F3/14 , C25F3/12 , G01B11/24 , H01L21/66 , B81C1/00
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
-
-
-
-
-
Search Results
6
records
(took 0.031 seconds)
