公开(公告)号：US20230411265A1

公开(公告)日：2023-12-21

申请号：US17844920

申请日：2022-06-21

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Ray Fredric De Asis ,  Tracee Kay De Asis

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49861 ,  H01L2224/48245 ,  H01L24/97 ,  H01L24/48 ,  H01L24/96

Abstract: An electronic device includes a package structure, a semiconductor die and a set of conductive leads, in which the package structure has a triangular shape with a bottom first side, a top second side and lateral third, fourth, and fifth sides. The set of conductive leads extend along the third side with one of the set of conductive leads electrically coupled to a conductive terminal of the semiconductor die, the package structure encloses a portion of the semiconductor die and portions of the set of conductive leads, and the package structure exposes further portions of the set of conductive leads along the first side and additional portions of the set of conductive leads along the third side.

公开(公告)号：US20240063107A1

公开(公告)日：2024-02-22

申请号：US17892202

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Jason Colte ,  Jerry Cayabyab ,  Julian Carlo Barbadillo ,  John Carlo Molina ,  Richard Sumalinog ,  Raust Glenn Magcaling ,  Ruby Ann Camenforte

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L21/561 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die mounted to the multilevel package substrate, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate. The multilevel package substrate has a first level, a second level, a first metal stack, and a second metal stack. The first metal stack includes a first set of contiguous metal structures of the first and second levels, the second metal stack includes a second set of contiguous metal structures of the first and second levels, the first and second metal stacks are spaced apart from one another, a first metal trace of the first metal stack partially overlaps a second metal trace of the second metal stack, and the first and second metal traces are in different levels of the multilevel package substrate.

公开(公告)号：US20230378146A1

公开(公告)日：2023-11-23

申请号：US18320102

申请日：2023-05-18

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Julian Carlo Barbadillo ,  Chun Ping Lo ,  Sylvester Ankamah-Kusi ,  Rajen Murugan ,  Thomas Kronenberg ,  Jonathan Noquil ,  Guangxu Li ,  Blake Travis ,  Jason Colte

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L23/49822 ,  H01L28/40 ,  H01L23/3121 ,  H01L24/16 ,  H01L23/49562 ,  H01L21/4857 ,  H01L21/56 ,  H01L2224/16227

Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.

公开(公告)号：US20240203801A1

公开(公告)日：2024-06-20

申请号：US18069224

申请日：2022-12-20

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Ray Fredric De Asis ,  Julian Carlo Barbadillo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48157

Abstract: An example semiconductor package comprises a semiconductor die having a top side with bond pads and a leadframe including a die attach pad. A bottom side of the semiconductor die is mounted on the die attach pad using a die attach material. The leadframe has at least one lead with a top surface and a bottom surface. At least one bond pad is coupled to the top surface of at least one lead by a bond wire. A mold compound covers the semiconductor die, the bond wires, and at least a portion of the at least one lead. A test pad is located on or adjacent to the bottom surface of the at least one lead. The test pad is electrically coupled to the at least one lead.

公开(公告)号：US20230197575A1

公开(公告)日：2023-06-22

申请号：US17711668

申请日：2022-04-01

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Ernesto P. Rafael, Jr. ,  Dolores B. Milo

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4828 ,  H01L23/49548 ,  H01L21/4842 ,  H01L24/48

Abstract: An integrated circuit package includes a die attach pad and a plurality of conductors formed from a lead frame material. A cavity is formed in a top surface of the die attach pad. A die attach adhesive is disposed within the cavity. A top surface of the die attach adhesive is flush with the top surface of the die attach pad. A semiconductor die is mounted on the die attach pad using the die attach adhesive. The semiconductor die is electrically connected to the plurality of conductors through a set of bond wires. A bottom surface of the semiconductor die is coplanar with the top surface of the die attach pad. A molding compound covers portions of the lead frame, the semiconductor die, and the set of bond wires.

公开(公告)号：US20240322786A1

公开(公告)日：2024-09-26

申请号：US18189388

申请日：2023-03-24

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Laura May Antoinette Dela Paz Clemente ,  Ray Fredric De Asis

IPC: H03H9/10 ,  H03H3/02 ,  H03H9/02 ,  H03H9/05

CPC classification number: H03H9/1042 ,  H03H3/02 ,  H03H9/02133 ,  H03H9/0523 ,  H03H9/0533 ,  H03H9/0547

Abstract: A semiconductor package comprises a leadframe having a die attach pad and one or more leads and a semiconductor die electrically connected to the die attach pad. A BAW device is attached to the semiconductor die. A mold compound surrounds the first semiconductor die and covers portions of the leadframe and a first portion of a top surface of the semiconductor die. The mold compound has a cavity area. The mold compound does not cover the BAW device or a second portion of the top surface of the semiconductor die in the cavity area. A glob top material is disposed within the cavity area. The glob top material covers the BAW device and the second portion of the top of the semiconductor die.

公开(公告)号：US20240105557A1

公开(公告)日：2024-03-28

申请号：US17951162

申请日：2022-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Laura May Antoinette Clemente ,  John Carlo Molina

IPC: H01L23/495 ,  H01L21/02 ,  H01L21/306 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/02098 ,  H01L21/306 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4952 ,  H01L24/43 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48177

Abstract: An electronic device includes a leadframe including a die pad and contacts, where a die attached is to the die pad. Wire bonds are attached from the die to the contacts and a mold compound overlies the leadframe and encapsulates the die and the wire bonds. The mold compound has angled side surfaces that extend from a top of the mold compound to a bonding surface of the contacts. The contacts extend from the angled side surfaces in a range of approximately 100 to 300 um.