公开(公告)号：US20240322786A1

公开(公告)日：2024-09-26

申请号：US18189388

申请日：2023-03-24

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Laura May Antoinette Dela Paz Clemente ,  Ray Fredric De Asis

IPC: H03H9/10 ,  H03H3/02 ,  H03H9/02 ,  H03H9/05

CPC classification number: H03H9/1042 ,  H03H3/02 ,  H03H9/02133 ,  H03H9/0523 ,  H03H9/0533 ,  H03H9/0547

Abstract: A semiconductor package comprises a leadframe having a die attach pad and one or more leads and a semiconductor die electrically connected to the die attach pad. A BAW device is attached to the semiconductor die. A mold compound surrounds the first semiconductor die and covers portions of the leadframe and a first portion of a top surface of the semiconductor die. The mold compound has a cavity area. The mold compound does not cover the BAW device or a second portion of the top surface of the semiconductor die in the cavity area. A glob top material is disposed within the cavity area. The glob top material covers the BAW device and the second portion of the top of the semiconductor die.

公开(公告)号：US20230411265A1

公开(公告)日：2023-12-21

申请号：US17844920

申请日：2022-06-21

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Ray Fredric De Asis ,  Tracee Kay De Asis

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49861 ,  H01L2224/48245 ,  H01L24/97 ,  H01L24/48 ,  H01L24/96

Abstract: An electronic device includes a package structure, a semiconductor die and a set of conductive leads, in which the package structure has a triangular shape with a bottom first side, a top second side and lateral third, fourth, and fifth sides. The set of conductive leads extend along the third side with one of the set of conductive leads electrically coupled to a conductive terminal of the semiconductor die, the package structure encloses a portion of the semiconductor die and portions of the set of conductive leads, and the package structure exposes further portions of the set of conductive leads along the first side and additional portions of the set of conductive leads along the third side.

公开(公告)号：US20250006683A1

公开(公告)日：2025-01-02

申请号：US18345065

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： John Carlo C Molina ,  Boom Rabilas ,  Ray Fredric De Asis

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: An electronic device includes a semiconductor die, a support structure and bond wires, where the semiconductor die has a semiconductor body, a metallization structure over the semiconductor body, and a conductive terminal, the metallization structure includes a top level that extends in a plane of orthogonal first and second directions, the conductive terminal extends away from the plane along an orthogonal third direction, and the support structure has a conductive metal feature with an attachment location. The bond wires are on the attachment location and a package structure at least partially encloses the semiconductor die and a portion of the support structure, where the conductive terminal is soldered to the attachment location of the conductive feature over at least some of the bond wires.

公开(公告)号：US20240203801A1

公开(公告)日：2024-06-20

申请号：US18069224

申请日：2022-12-20

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Ray Fredric De Asis ,  Julian Carlo Barbadillo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48157

Abstract: An example semiconductor package comprises a semiconductor die having a top side with bond pads and a leadframe including a die attach pad. A bottom side of the semiconductor die is mounted on the die attach pad using a die attach material. The leadframe has at least one lead with a top surface and a bottom surface. At least one bond pad is coupled to the top surface of at least one lead by a bond wire. A mold compound covers the semiconductor die, the bond wires, and at least a portion of the at least one lead. A test pad is located on or adjacent to the bottom surface of the at least one lead. The test pad is electrically coupled to the at least one lead.

公开(公告)号：US20240128228A1

公开(公告)日：2024-04-18

申请号：US17971730

申请日：2022-10-24

Applicant: Texas Instruments Incorporated

Inventor： Aniceto Rabilas, JR. ,  Ray Fredric De Asis ,  Jason Colte

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/85 ,  H01L24/45 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48175 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/85986

Abstract: An electronic device includes a package structure, a conductive terminal exposed outside the package structure, a semiconductor die in the package structure, and a bond wire having contiguous first and second portions. The first portion has a first end and a second end, the first end connected to the semiconductor die by a first bond and the second end connected to the conductive terminal by a second bond. The second portion has a first end and a second end, the first end of the second portion connected to the second end of the first portion, and the second end of the second portion connected to the conductive terminal by a third bond.