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公开(公告)号：US11239130B2
公开(公告)日：2022-02-01
申请号：US16597915
申请日：2019-10-10
Applicant: Texas Instruments Incorporated
IPC: H01L23/31 , H01L23/00 , H01L23/495 , H01L21/56 , H01L25/00
Abstract: A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.
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公开(公告)号：US09039427B2
公开(公告)日：2015-05-26
申请号：US13767009
申请日：2013-02-14
Applicant: Texas Instruments Incorporated
CPC classification number: H05K3/3442 , H01G2/065 , H01G4/232 , H01G4/30 , H05K1/18 , H05K1/183 , H05K3/0014 , H05K3/301 , H05K3/3452 , H05K2201/0162 , H05K2201/09036 , H05K2201/09172 , H05K2201/09909 , H05K2203/0126 , H05K2203/046 , H05K2203/167 , H05K2203/168 , Y02P70/613 , Y10T29/43 , Y10T29/49135
Abstract: An interdigitated chip capacitor (“IDC”) assembly including an IDC having a semiconductor block with a top portion, a bottom portion opposite the top portion, a plurality of sidewall portions extending between the top and bottom portions, and a plurality of terminals located on the sidewall portions; and a substrate having a top portion with a plurality of generally flat, vertically extending, nonconductive abutment surfaces thereon, the sidewall portions of the IDC being abuttingly engaged with at least some of the plurality of abutment surfaces.
Abstract translation: 一种交错式片状电容器（“IDC”）组件，包括具有顶部的半导体块的IDC，与顶部相对的底部，在顶部和底部之间延伸的多个侧壁部分，以及位于 侧壁部分; 以及具有在其上具有多个大致平坦的，垂直延伸的非导电邻接表面的顶部的基底，所述IDC的侧壁部分与多个邻接表面中的至少一些邻接地接合。
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公开(公告)号：US09564410B2
公开(公告)日：2017-02-07
申请号：US14793813
申请日：2015-07-08
Applicant: Texas Instruments Incorporated
Inventor： Floro Lopez Camenforte, III , James Raymond Maliclic Baello , Armando Tresvalles Clarina, Jr.
IPC: H01L21/50 , H01L21/48 , H01L23/498 , H01L23/00 , H01L21/768 , H01L21/78
CPC classification number: H01L24/13 , H01L21/4853 , H01L21/76834 , H01L21/78 , H01L23/49844 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/94 , H01L2224/0345 , H01L2224/0346 , H01L2224/036 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05541 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/0569 , H01L2224/1145 , H01L2224/1146 , H01L2224/116 , H01L2224/13005 , H01L2224/13007 , H01L2224/13016 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/16245 , H01L2224/81191 , H01L2224/814 , H01L2224/94 , H01L2924/01022 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/2064 , H01L2924/3512 , H01L2924/00014 , H01L2924/013 , H01L2924/014 , H01L2224/11 , H01L2224/03 , H01L2924/207
Abstract: A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.
Abstract translation: 一种半导体器件，具有端子部位（100），该端子部位（100）包括由电介质材料层（130）覆盖的第一金属的平坦焊盘（110），所述焊盘上方的层平行于焊盘并具有第一直径的窗口 132）暴露下面的垫的表面。 终端位置还具有覆盖暴露的第一金属的表面的第二金属的片状膜（140）和构成窗口的电介质层的环的表面，膜片具有更大的第二直径（141） 比第一个直径; 以及附着在所述膜上的第三金属的凸块（150），所述凸块具有比所述第二直径小的第三直径（151），由此所述膜从所述凸块凸出成凸缘。
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Patent Agency Ranking
公开(公告)号：US20170012012A1
公开(公告)日：2017-01-12
申请号：US14793813
申请日：2015-07-08
Applicant: Texas Instruments Incorporated
Inventor： Floro Lopez Camenforte, III , James Raymond Maliclic Baello , Armando Tresvalles Clarina, JR.
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L21/4853 , H01L21/76834 , H01L21/78 , H01L23/49844 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/94 , H01L2224/0345 , H01L2224/0346 , H01L2224/036 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05541 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/0569 , H01L2224/1145 , H01L2224/1146 , H01L2224/116 , H01L2224/13005 , H01L2224/13007 , H01L2224/13016 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/16245 , H01L2224/81191 , H01L2224/814 , H01L2224/94 , H01L2924/01022 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/2064 , H01L2924/3512 , H01L2924/00014 , H01L2924/013 , H01L2924/014 , H01L2224/11 , H01L2224/03 , H01L2924/207
Abstract: A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.
Abstract translation: 一种半导体器件，具有端子部位（100），该端子部位（100）包括由电介质材料层（130）覆盖的第一金属的平坦焊盘（110），所述焊盘上方的层平行于焊盘并具有第一直径的窗口 132）暴露下面的垫的表面。 终端位置还具有覆盖暴露的第一金属的表面的第二金属的片状膜（140）和构成窗口的电介质层的环的表面，膜片具有更大的第二直径（141） 比第一个直径; 以及附着在所述膜上的第三金属的凸块（150），所述凸块具有比所述第二直径小的第三直径（151），由此所述膜从所述凸块凸出成凸缘。
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公开(公告)号：US09468107B2
公开(公告)日：2016-10-11
申请号：US14695216
申请日：2015-04-24
Applicant: Texas Instruments Incorporated
CPC classification number: H05K3/3442 , H01G2/065 , H01G4/232 , H01G4/30 , H05K1/18 , H05K1/183 , H05K3/0014 , H05K3/301 , H05K3/3452 , H05K2201/0162 , H05K2201/09036 , H05K2201/09172 , H05K2201/09909 , H05K2203/0126 , H05K2203/046 , H05K2203/167 , H05K2203/168 , Y02P70/613 , Y10T29/43 , Y10T29/49135
Abstract: A method of registering terminals on an interdigitated chip capacitor (“IDC”) with a plurality of contact pads on a substrate. At least one vertically extending nonconductive abutment surface is formed between adjacent ones of the contact pads. A plurality of grooves projecting outwardly from said a central recess is formed on the substrate top portion. At least one sidewall portion of the IDC is urged into abutting engagement with the at least one abutment surface on the substrate. Another method prevent solder from causing short circuits between adjacent terminals. A plurality of grooves extending laterally outwardly from a central recessed portion are formed. The plurality of grooves defining a plurality of inwardly projecting fingers. A plurality of contact pads on are formed on a respective plurality of fingers. A solder bead is formed on at least some of the plurality of contact pads. The at least one solder bead is isolated from adjacent solder beads and adjacent terminals.
Abstract translation: 一种在叉指片式电容器（“IDC”）上的端子与衬底上的多个接触焊盘对准的方法。 在相邻的接触垫之间形成至少一个垂直延伸的非导电邻接表面。 在所述基板顶部形成有从所述中心凹部向外突出的多个凹槽。 IDC的至少一个侧壁部分被推动成与基底上的至少一个邻接表面邻接接合。 另一种方法可以防止焊料在相邻端子之间引起短路。 形成从中心凹部横向向外延伸的多个槽。 多个槽限定多个向内突出的指状物。 在多个指状物上形成多个接触垫。 在多个接触垫中的至少一些上形成焊珠。 至少一个焊珠与相邻的焊球和相邻的端子隔离。
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公开(公告)号：US20210111086A1
公开(公告)日：2021-04-15
申请号：US16597915
申请日：2019-10-10
Applicant: Texas Instruments Incorporated
IPC: H01L23/31 , H01L23/00 , H01L23/495 , H01L21/56 , H01L25/00
Abstract: A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.
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公开(公告)号：US20150230345A1
公开(公告)日：2015-08-13
申请号：US14695216
申请日：2015-04-24
Applicant: Texas Instruments Incorporated
CPC classification number: H05K3/3442 , H01G2/065 , H01G4/232 , H01G4/30 , H05K1/18 , H05K1/183 , H05K3/0014 , H05K3/301 , H05K3/3452 , H05K2201/0162 , H05K2201/09036 , H05K2201/09172 , H05K2201/09909 , H05K2203/0126 , H05K2203/046 , H05K2203/167 , H05K2203/168 , Y02P70/613 , Y10T29/43 , Y10T29/49135
Abstract: A method of registering terminals on an interdigitated chip capacitor (“IDC”) with a plurality of contact pads on a substrate. At least one vertically extending nonconductive abutment surface is formed between adjacent ones of the contact pads. A plurality of grooves projecting outwardly from said a central recess is formed on the substrate top portion. At least one sidewall portion of the IDC is urged into abutting engagement with the at least one abutment surface on the substrate. Another method prevent solder from causing short circuits between adjacent terminals. A plurality of grooves extending laterally outwardly from a central recessed portion are formed. The plurality of grooves defining a plurality of inwardly projecting fingers. A plurality of contact pads on are formed on a respective plurality of fingers. A solder bead is formed on at least some of the plurality of contact pads. The at least one solder bead is isolated from adjacent solder beads and adjacent terminals.
Abstract translation: 一种在叉指片式电容器（“IDC”）上的端子与衬底上的多个接触焊盘对准的方法。 在相邻的接触垫之间形成至少一个垂直延伸的非导电邻接表面。 在所述基板顶部形成有从所述中心凹部向外突出的多个凹槽。 IDC的至少一个侧壁部分被推动成与基底上的至少一个邻接表面邻接接合。 另一种方法可以防止焊料在相邻端子之间引起短路。 形成从中心凹部横向向外延伸的多个槽。 多个槽限定多个向内突出的指状物。 在多个指状物上形成多个接触垫。 在多个接触垫中的至少一些上形成焊珠。 至少一个焊珠与相邻的焊球和相邻的端子隔离。
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公开(公告)号：US20140227891A1
公开(公告)日：2014-08-14
申请号：US13767009
申请日：2013-02-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H05K3/3442 , H01G2/065 , H01G4/232 , H01G4/30 , H05K1/18 , H05K1/183 , H05K3/0014 , H05K3/301 , H05K3/3452 , H05K2201/0162 , H05K2201/09036 , H05K2201/09172 , H05K2201/09909 , H05K2203/0126 , H05K2203/046 , H05K2203/167 , H05K2203/168 , Y02P70/613 , Y10T29/43 , Y10T29/49135
Abstract: An interdigitated chip capacitor (“IDC”) assembly including an IDC having a semiconductor block with a top portion, a bottom portion opposite the top portion, a plurality of sidewall portions extending between the top and bottom portions, and a plurality of terminals located on the sidewall portions; and a substrate having a top portion with a plurality of generally flat, vertically extending, nonconductive abutment surfaces thereon, the sidewall portions of the IDC being abuttingly engaged with at least some of the plurality of abutment surfaces.
Abstract translation: 一种交错式片状电容器（“IDC”）组件，包括具有顶部的半导体块的IDC，与顶部相对的底部，在顶部和底部之间延伸的多个侧壁部分，以及位于 侧壁部分; 以及具有在其上具有多个大致平坦的，垂直延伸的非导电邻接表面的顶部的基底，所述IDC的侧壁部分与多个邻接表面中的至少一些邻接地接合。
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