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    Semiconductor memory device having disturb test circuit
    1.
    发明授权
    Semiconductor memory device having disturb test circuit 失效
    具有干扰测试电路的半导体存储器件

    公开(公告)号：US06552939B1

    公开(公告)日：2003-04-22

    申请号：US09976116

    申请日：2001-10-15

    申请人： Takeo Miki ,  Kiyohiro Furutani

    发明人： Takeo Miki ,  Kiyohiro Furutani

    IPC分类号： G11C2900

    CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C29/50

    摘要： In a semiconductor memory device having normal circuit blocks (NBL) and a redundant circuit block (RBL) for replacement, a test mode setting unit (14, 19) sets a spare non-selection mode (TMSPROFF) and enables to restore an original address of a normal circuit (DE) in a state before executing a replacement to thereby implement a disturb test even after the replacement.

    摘要翻译： 在具有正常电路块（NBL）和用于替换的冗余电路块（RBL）的半导体存储器件中，测试模式设置单元（14,19）设置备用非选择模式（TMSPROFF）并使能够恢复原始地址 在执行替换之前的状态下的正常电路（DE），从而即使在更换之后也执行干扰测试。

    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode
    2.
    发明授权
    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode 有权
    具有以正常模式提供过驱动电压并在刷新模式下被提供降压电压的读出放大器的半导体器件

    公开(公告)号：US08300480B2

    公开(公告)日：2012-10-30

    申请号：US12897399

    申请日：2010-10-04

    申请人： Kiyohiro Furutani

    发明人： Kiyohiro Furutani

    IPC分类号： G11C7/08

    CPC分类号： G11C11/4074 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4068

    摘要： A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.

    摘要翻译： 具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于 外部电源电压和降压电路将外部电源电压降低到第二电压。 为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。 在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

    Semiconductor device with refresh control circuit
    3.
    发明申请
    Semiconductor device with refresh control circuit 失效
    具有刷新控制电路的半导体器件

    公开(公告)号：US20100157713A1

    公开(公告)日：2010-06-24

    申请号：US12654109

    申请日：2009-12-10

    申请人： Kiyohiro Furutani

    发明人： Kiyohiro Furutani

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C11/406 ,  G11C8/06 ,  G11C8/08 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4067

    摘要： In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

    摘要翻译： 在包括具有待机状态和活动状态的电流降低电路的基于行的控制电路的半导体器件中，刷新控制电路在自刷新模式下以预定的时间间隔生成刷新请求信号，并且时间顺序地产生 与刷新请求信号一次的N次内部有效信号。 基于行的控制电路基于N次内部有效信号时间顺序刷新存储单元的信息。 刷新控制电路通过使电流还原电路处于待机状态来使基于行的控制电路失活。

    Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
    8.
    发明授权
    Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein 失效
    允许在其中令人满意地重写数据的同步半导体存储器件

    公开(公告)号：US06477109B2

    公开(公告)日：2002-11-05

    申请号：US09922669

    申请日：2001-08-07

    申请人： Kiyohiro Furutani ,  Yasuhiro Konishi

    发明人： Kiyohiro Furutani ,  Yasuhiro Konishi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076

    摘要： In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

    摘要翻译： 在SDRAM中，在读出放大器激活信号变为高电平之后经过预定时间段后引入控制信号变为有效低电平。 当突发期间的信号变为高电平，并且控制信号也变低时，字线被丢弃，未选择为低电平。 这样，成对的位线可以具有充分放大的电位差，以使数据能够令人满意地重写到存储单元中。

    Semiconductor memory device and method of checking same for defect
    9.
    发明授权
    Semiconductor memory device and method of checking same for defect 失效
    半导体存储器件及其检查方法为缺陷

    公开(公告)号：US06400621B2

    公开(公告)日：2002-06-04

    申请号：US09912518

    申请日：2001-07-26

    申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

    发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

    IPC分类号： G11C700

    CPC分类号： G11C29/24

    摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

    摘要翻译： 一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器 正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。 控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。 所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

    Semiconductor device having an internal voltage generating circuit
    10.
    发明授权
    Semiconductor device having an internal voltage generating circuit 失效
    具有内部电压产生电路的半导体器件

    公开(公告)号：US06297624B1

    公开(公告)日：2001-10-02

    申请号：US09258159

    申请日：1999-02-26

    申请人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

    发明人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

    IPC分类号： G05F316

    CPC分类号： G05F1/465

    摘要： An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.

    摘要翻译： 内部电源电路从外部电源电压产生内部电源电压。 电压电平控制电路控制由内部电源电路产生的内部电源电压的电压电平和温度特性。 内部电源电路在低温区域产生具有负温度或零温度特性的内部电源电压，在高温区域产生正温度特性。 电压电平控制电路包括优化用于驱动读出放大器电路的感测电源线稳定电容的电容值的结构，确定内部电源电路的外部电源电压的最低可操作区域的电平转换电路，或 一个在上电时强制运行内部降压转换器的结构。 以小的占用面积和低的电流消耗稳定地产生期望的内部电源电压。