公开(公告)号：US20120139024A1

公开(公告)日：2012-06-07

申请号：US13050297

申请日：2011-03-17

Applicant: Takayuki TOBA ,  Tohru Ozaki

Inventor： Takayuki TOBA ,  Tohru Ozaki

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/66825

Abstract: In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

Abstract translation: 在一个实施例中，非易失性半导体存储器包括存储单元阵列，第一氮化硅膜和第二氮化硅膜。 存储单元阵列包括NAND单元单元。 每个NAND单元单元具有存储单元晶体管，源极选择栅极晶体管和漏极侧选择栅极晶体管。 源极侧选择栅极晶体管以彼此面对的方式设置，并且漏极侧选择栅极晶体管以彼此面对的方式设置。 第一氮化硅膜存在于源极选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。 第二氮化硅膜形成在漏极侧选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。

公开(公告)号：US20090278187A1

公开(公告)日：2009-11-12

申请号：US12406481

申请日：2009-03-18

Applicant: Takayuki TOBA

Inventor： Takayuki TOBA

IPC: H01L29/788 ,  H01L21/336 ,  H01L29/792

CPC classification number: H01L29/42324 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/4234

Abstract: A semiconductor device of an aspect of the present invention includes a semiconductor substrate, two diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a channel region between the two diffusion layers, and a gate electrode which is composed of a stack of a plurality of conductive films and a plurality of insulating films provided on the gate insulating film and a silicide layer provided on the stack, wherein of the plurality of films included in the stack, the conductive film different in configuration from the silicide layer is in contact with the gate insulating film.

Abstract translation: 本发明的半导体器件包括半导体衬底，设置在半导体衬底中的两个扩散层，设置在两个扩散层之间的沟道区上的栅极绝缘膜以及由一堆 设置在栅极绝缘膜上的多个导电膜和多个绝缘膜和设置在堆叠上的硅化物层，其中在堆叠中包括的多个膜中，与硅化物层不同的导电膜接触 与栅极绝缘膜。

公开(公告)号：US20110241095A1

公开(公告)日：2011-10-06

申请号：US13051784

申请日：2011-03-18

Applicant: Kikuko SUGIMAE ,  Takayuki TOBA

Inventor： Kikuko SUGIMAE ,  Takayuki TOBA

IPC: H01L29/788 ,  H01L21/76

CPC classification number: H01L27/11521 ,  H01L21/76895 ,  H01L27/11519 ,  H01L27/11524

Abstract: In one embodiment, a semiconductor memory device, including a memory cell having a floating gate electrode above a semiconductor substrate via a first gate insulator and a control gate electrode above the floating gate electrode via a first inter-gate insulator, a contact electrode having a bottom electrode contacted to an upper surface of the semiconductor substrate, top electrodes via a second inter-gate insulators on both edge portions of the bottom electrode and a plug electrode between the top electrodes, the plug electrode contacted to an upper surface of the bottom electrode.

Abstract translation: 在一个实施例中，一种半导体存储器件，包括经由第一栅极绝缘体在半导体衬底上方具有浮置栅电极的存储器单元和经由第一栅极间绝缘体在浮置栅极上方的控制栅极电极，具有 底部电极与半导体衬底的上表面接触，顶部电极经由底部电极的两个边缘部分上的第二栅极间绝缘体和顶部电极之间的插塞电极，插头电极与底部电极的上表面接触 。

公开(公告)号：US20100270606A1

公开(公告)日：2010-10-28

申请号：US12765477

申请日：2010-04-22

Applicant: Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

Inventor： Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract translation: 在存储单元阵列区域周围形成外围电路区域。 外围电路区域具有元件区域，隔离元件区域的元件隔离区域和形成在每个元件区域中并包括在沟道宽度方向上延伸的栅电极的场效应晶体管。 栅电极的端部和角部位于元件隔离区上。 栅电极的角部的曲率半径比从沟道宽度方向的元件区域的端部到沟道宽度方向的栅电极的端部的长度小，并且小于85nm 。

公开(公告)号：US20100237399A1

公开(公告)日：2010-09-23

申请号：US12711512

申请日：2010-02-24

Applicant: Takayuki TOBA

Inventor： Takayuki TOBA

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11526 ,  H01L27/11546

Abstract: A semiconductor memory device includes: a semiconductor substrate; a plurality of device isolation regions being disposed in an upper-layer portion of the semiconductor substrate, and dividing the upper-layer portion into a plurality of semiconductor portions extending in a first direction; a plurality of charge storage films which are disposed on one of the plurality of the semiconductor portions and spaced apart from one another in the first direction; a block insulating film disposed covering the plurality of charge storage films; and a word electrode disposed on the block insulating film for each of rows of the plurality of charge storage films arranged in a second direction intersecting the first direction, wherein the block insulating film is disposed continuously in the first direction and in the second direction.

Abstract translation: 半导体存储器件包括：半导体衬底; 多个器件隔离区设置在半导体衬底的上层部分中，并且将上层部分分割成沿第一方向延伸的多个半导体部分; 多个电荷存储膜，其设置在所述多个半导体部分中的一个上，并且在所述第一方向上彼此间隔开; 覆盖所述多个电荷存储膜的块绝缘膜; 以及在与所述第一方向交叉的第二方向上配置的所述多个电荷存储膜中的每一行的所述块绝缘膜上配置的字电极，其中，所述块绝缘膜沿所述第一方向和所述第二方向连续配置。

公开(公告)号：US20130087844A1

公开(公告)日：2013-04-11

申请号：US13405570

申请日：2012-02-27

Applicant: Takayuki TOBA

Inventor： Takayuki TOBA

IPC: H01L29/788

CPC classification number: H01L29/792 ,  H01L21/76897 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: A semiconductor device includes: a semiconductor substrate; an element isolation insulator; an insulating block; an interlayer insulating film; and a contact. A plurality of active areas extending in one direction and protruding upward are formed at an upper surface of the substrate. The insulating block is disposed directly on the element isolation insulator. The contact is formed in the interlayer insulating film. A lower end of the contact is connected to an upper surface of the active area. A part of a lower surface of the contact located directly on the insulating block is positioned higher than a part of a lower surface of the contact located directly on the active area.

Abstract translation: 半导体器件包括：半导体衬底; 元件隔离绝缘子; 绝缘块; 层间绝缘膜; 和联系人。 在基板的上表面形成有沿一个方向延伸并向上突出的多个有效区域。 绝缘块直接设置在元件绝缘体上。 在层间绝缘膜中形成接触。 接触件的下端连接到有源区域的上表面。 直接位于绝缘块上的接触件的下表面的一部分定位成高于直接位于有效区域上的触头的下表面的一部分。

公开(公告)号：US20110069524A1

公开(公告)日：2011-03-24

申请号：US12821585

申请日：2010-06-23

Applicant: Takayuki TOBA ,  Hiroyuki Nitta

Inventor： Takayuki TOBA ,  Hiroyuki Nitta

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C8/14 ,  G11C13/0007 ,  G11C13/004 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72

Abstract: A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.

Abstract translation: 半导体存储器件包括控制电路。 控制电路将第一电压施加到上部互连中的所选择的一个中，将第二电压施加到未选择的上部互连中的一个，将第三电压施加到第一虚拟上部互连并独立地控制要设置的第一至第三电压 到不同的值。

公开(公告)号：US20090278195A1

公开(公告)日：2009-11-12

申请号：US12406367

申请日：2009-03-18

Applicant: Takayuki TOBA

Inventor： Takayuki TOBA

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823857

Abstract: A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film formed on the first insulating film. The control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film. The first MOS transistor includes a second conductive film, a second metal film, a third conductive film, and a second diffusion layer. The second conductive film formed on a second active region. The second metal film formed on the second conductive film. The third conductive film formed on a second metal film.

Abstract translation: 半导体存储器件包括存储单元晶体管和第一MOS晶体管。 存储单元晶体管包括第一绝缘膜，第二绝缘膜，控制栅电极和第一扩散层。 形成在第一有源区上的第一绝缘膜。 形成在第一绝缘膜上的第二绝缘膜。 形成为包括形成在第二绝缘膜上的第一金属膜和形成在第一金属膜上的第一导电膜的控制栅电极。 第一MOS晶体管包括第二导电膜，第二金属膜，第三导电膜和第二扩散层。 形成在第二有源区上的第二导电膜。 形成在第二导电膜上的第二金属膜。 形成在第二金属膜上的第三导电膜。

公开(公告)号：US20070155096A1

公开(公告)日：2007-07-05

申请号：US11616167

申请日：2006-12-26

Applicant: Takayuki TOBA

Inventor： Takayuki TOBA

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween. The interelectrode insulating film covers whole side portions of the floating gate electrode located in a direction different from a direction in which the word line extends, and the control gate electrode covers the side portions of the floating gate electrode located in the direction different from the direction in which the word line extends.

Abstract translation: 非易失性半导体存储器包括第一和第二扩散层区域，在第一和第二扩散层区域之间的沟道区域上布置有栅极绝缘膜的浮栅，以及用作字的控制栅电极 并且布置在浮置栅电极上，其间插入有电极间绝缘膜。 电极间绝缘膜覆盖位于与字线延伸的方向不同的方向的浮栅的整个侧部，并且控制栅电极覆盖浮置栅电极的与方向不同的方向的侧部 字线延伸。