公开(公告)号：US06496441B2

公开(公告)日：2002-12-17

申请号：US09907743

申请日：2001-07-19

Applicant: Takashi Kono ,  Tetsuo Kato

Inventor： Takashi Kono ,  Tetsuo Kato

IPC: G11C800

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C8/12

Abstract: By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

Abstract translation: 通过设计围绕芯片的中心区域的存储器阵列的布置，可以减少数据总线的总长度。 存储器阵列被布置成使得位于相对于中心区域点对称的位置的两个存储器阵列之一对应于较低的DQ端子，而另一个存储器阵列对应于上部DQ端子。 优选地，对应于上部DQ端子的存储器阵列和对应于下部DQ端子的存储器阵列各自集中地定位。 因此，可以提供在数据总线上具有改善的数据传播特性的半导体存储器件。

公开(公告)号：US09231242B2

公开(公告)日：2016-01-05

申请号：US13927462

申请日：2013-06-26

Applicant: Atsushi Sugihara ,  Takashi Kono ,  Tsubasa Matsuda ,  Naoyuki Wada ,  Shuji Tsutsumi ,  Tatsuya Hashimoto

Inventor： Atsushi Sugihara ,  Takashi Kono ,  Tsubasa Matsuda ,  Naoyuki Wada ,  Shuji Tsutsumi ,  Tatsuya Hashimoto

IPC: H01M4/04 ,  H01M4/1393 ,  H01M4/62

CPC classification number: H01M4/04 ,  H01M4/1393 ,  H01M4/62 ,  Y02E60/122 ,  Y02P70/54

Abstract: A method for producing a non-aqueous electrolyte secondary battery includes: subjecting a mixture of a negative-electrode active material on which oil has been adsorbed, CMC and water to hard kneading to prepare a primary kneaded mixture; diluting the primary kneaded mixture with water to prepare a slurry; and adding a binder to the slurry. The method further includes defining an amount of the oil to a value equal to or more than 50 ml/100 g and equal to or less than 62 ml/100 g, wherein the amount of the oil is an amount at the time when the viscosity characteristics of the negative-electrode active material exhibits 70% of the maximum torque that is generated when the oil is titrated onto the negative-electrode active material. The 1% aqueous solution viscosity of the CMC is defined to a value equal to or more than 6000 mPa·s and equal to or less than 8000 mPa·s.

Abstract translation: 一种非水电解质二次电池的制造方法，其特征在于，将具有吸附油的负极活性物质与CMC和水的混合物进行硬质混炼，制备初级混炼物; 用水稀释初级捏合混合物以制备浆料; 并向浆料中加入粘合剂。 该方法还包括将油的量定义为等于或大于50ml / 100g且等于或小于62ml / 100g的值，其中所述油的量是当粘度 负极活性物质的特性表现出当将油滴定在负极活性物质上时产生的最大扭矩的70％。 CMC的1％水溶液粘度定义为等于或大于6000mPa·s且等于或小于8000mPa·s的值。

公开(公告)号：US08774521B2

公开(公告)日：2014-07-08

申请号：US13404470

申请日：2012-02-24

Applicant: Yamato Kanda ,  Makoto Kitamura ,  Takashi Kono ,  Masashi Hirota

Inventor： Yamato Kanda ,  Makoto Kitamura ,  Takashi Kono ,  Masashi Hirota

IPC: G06K9/66 ,  G06T7/00

CPC classification number: G06T7/0012 ,  G06T2207/20036 ,  G06T2207/30021 ,  G06T2207/30096

Abstract: An image processing apparatus includes an approximate-surface calculator that calculates multiple approximate surfaces that each approximate the pixel value of a pixel included in an examination-target region of an image; an approximate-surface selector that selects at least one approximate surface from the approximate surfaces on the basis of the relation between the pixel value of the pixel in the examination-target region and the approximate surfaces; an approximate-region setting unit that sets an approximate region that is approximated by at least the selected one approximate surface; and an abnormal-region detector that detects an abnormal region on the basis of the pixel value of a pixel in the approximate region and the value corresponding to the coordinates of that pixel on at least one approximate surface.

Abstract translation: 一种图像处理装置，包括近似表面计算器，其计算出近似所述图像的检查对象区域中包含的像素的像素值的多个近似面; 基于检查对象区域中的像素的像素值与近似表面之间的关系，从近似表面选择至少一个近似表面的近似表面选择器; 近似区域设置单元，其设置至少所选择的一个近似表面近似的近似区域; 以及异常区域检测器，其基于近似区域中的像素的像素值检测异常区域，并且在至少一个近似表面上对应于该像素的坐标值。

公开(公告)号：US07376016B2

公开(公告)日：2008-05-20

申请号：US11488621

申请日：2006-07-19

Applicant: Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

Inventor： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/3459

Abstract: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

Abstract translation: 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US07339833B2

公开(公告)日：2008-03-04

申请号：US11481782

申请日：2006-07-07

Applicant: Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

Inventor： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

Abstract: Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.

Abstract translation: 使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。 电容元件的电容值根据写入数据的值而变化。 实现了以高精度写入多值数据的非易失性半导体存储器件。

公开(公告)号：US07135754B2

公开(公告)日：2006-11-14

申请号：US10757643

申请日：2004-01-13

Applicant: Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

Inventor： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

IPC: H01L23/48 ,  H05K7/06 ,  H01G4/228 ,  H01G9/04 ,  H09G9/012

CPC classification number: H01G9/012 ,  H01G9/042 ,  H01G9/10 ,  H01L2924/0002 ,  Y10S257/924 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  H01L2924/00

Abstract: In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

公开(公告)号：US07102953B2

公开(公告)日：2006-09-05

申请号：US11030185

申请日：2005-01-07

Applicant: Takashi Kono ,  Hironori Iga

Inventor： Takashi Kono ,  Hironori Iga

IPC: G11C5/14

CPC classification number: G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

Abstract: A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

Abstract translation: 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，从而可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

公开(公告)号：US06894940B2

公开(公告)日：2005-05-17

申请号：US10625588

申请日：2003-07-24

Applicant: Takashi Kono ,  Takeshi Hamamoto

Inventor： Takashi Kono ,  Takeshi Hamamoto

IPC: H01L21/8242 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/4097 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

Abstract: A sense amplifier driving line is connected to the source of an N-channel MOS transistor. Accordingly, even if a control signal attains H level, a sub-amplifier will not operate. This is because the sense amplifier driving line and an LIO line pair both attain a precharge potential, and a gate-source voltage of an N-channel MOS transistor attains 0V. Thus, it is not necessary to add a circuit configuration for supplying a signal notifying of activation of a row block, and a semiconductor memory device with a smaller area is obtained.

Abstract translation: 读出放大器驱动线连接到N沟道MOS晶体管的源极。 因此，即使控制信号达到H电平，子放大器也不会运行。 这是因为读出放大器驱动线和LIO线对都达到预充电电位，并且N沟道MOS晶体管的栅极 - 源极电压达到0V。 因此，不需要添加用于提供通知行块的激活的信号的电路配置，并且获得具有较小面积的半导体存储器件。

公开(公告)号：US06753720B2

公开(公告)日：2004-06-22

申请号：US10302849

申请日：2002-11-25

Applicant: Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

Inventor： Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

IPC: G05F110

CPC classification number: G05F1/465 ,  G11C5/143 ,  G11C5/145

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract translation: 为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态 初始控制电路。

公开(公告)号：US06741521B2

公开(公告)日：2004-05-25

申请号：US10253928

申请日：2002-09-25

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G11C800

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/107

Abstract: Data of 2-bits prefetched from a memory array and transmitted to an amplifying circuit via a data bus is ordered in accordance with the least significant bit of a column address which is a start address supplied from the outside. The first data is output to read data buses and is directly transmitted to an output data latch. The second data is held once by a second data latch and, after that, transmitted to the output data latch. Since the first data is transmitted from the amplifying circuit directly to the output data latch, the time from a read command is received until data is started to be output can be shortened.

Abstract translation: 根据从外部提供的起始地址的列地址的最低有效位来排序从存储器阵列预取并经由数据总线发送到放大电路的2位的数据。 第一数据被输出以读取数据总线，并直接发送到输出数据锁存器。 第二数据由第二数据锁存器保持一次，之后被发送到输出数据锁存器。 由于第一数据从放大电路直接发送到输出数据锁存器，所以从读取命令开始的时间直到数据开始输出才能被缩短。