公开(公告)号：US20240389314A1

公开(公告)日：2024-11-21

申请号：US18788674

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Shun-Neng Wang ,  Tung-Huang Chen ,  Ching-Hung Kao

IPC: H10B41/10 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

公开(公告)号：US20230307366A1

公开(公告)日：2023-09-28

申请号：US18328916

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chun Wang ,  Tzy-Kuang Lee ,  Chih-Hsien Lin ,  Ching-Hung Kao ,  Yen-Yu Chen

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/53238 ,  H01L23/5223 ,  H01L23/3171 ,  H01L23/291 ,  H01L21/76871 ,  H01L23/5283 ,  H01L21/56 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5226

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

公开(公告)号：US20230119077A1

公开(公告)日：2023-04-20

申请号：US17586685

申请日：2022-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hung Kao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

Abstract: A semiconductor device includes an active gate metal structure disposed over a substrate, the active gate metal structure having a first sidewall and a second sidewall opposite to each other. The semiconductor device includes a first source/drain region disposed adjacent the first sidewall of the active gate metal structure with a first lateral distance. The semiconductor device includes a second source/drain region disposed adjacent the second sidewall of the active gate metal structure with a second lateral distance, wherein the second lateral distance is substantially greater than the first lateral distance. The semiconductor device includes a resist protective oxide (RPO) comprising a first portion extending over a portion of a major surface of the substrate that is laterally located between the second sidewall and the second source/drain region, wherein the RPO has no portion extending over a top surface of the active gate metal structure.

公开(公告)号：US20230016468A1

公开(公告)日：2023-01-19

申请号：US17584814

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hung Kao

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a recess along a top surface of a semiconductor substrate. The method includes forming a nitride-based spacer layer extending along a first sidewall of the recess. The method includes forming a field oxide layer in the recess extending along a bottom surface of the recess, while a lateral tip of the field oxide layer is blocked from extending into any portion of the semiconductor substrate other than the recess by the nitride-based spacer layer.

公开(公告)号：US12165997B2

公开(公告)日：2024-12-10

申请号：US17711705

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hung Kao ,  Kuei-Yu Deng

IPC: H01L23/00

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

公开(公告)号：US11670594B2

公开(公告)日：2023-06-06

申请号：US17308321

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chun Wang ,  Tzy-Kuang Lee ,  Chih-Hsien Lin ,  Ching-Hung Kao ,  Yen-Yu Chen

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/53238 ,  H01L21/56 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76871 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

公开(公告)号：US20230026305A1

公开(公告)日：2023-01-26

申请号：US17711705

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hung Kao ,  Kuei-Yu Deng

IPC: H01L23/00

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

公开(公告)号：US11380721B2

公开(公告)日：2022-07-05

申请号：US16790386

申请日：2020-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Yu Wei ,  Fu-Cheng Chang ,  Hsin-Chi Chen ,  Ching-Hung Kao ,  Chia-Pin Cheng ,  Kuo-Cheng Lee ,  Hsun-Ying Huang ,  Yen-Liang Lin

IPC: H01L29/78 ,  H01L27/146 ,  H01L29/423 ,  H01L29/06

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US10566361B2

公开(公告)日：2020-02-18

申请号：US15591689

申请日：2017-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Yu Wei ,  Fu-Cheng Chang ,  Hsin-Chi Chen ,  Ching-Hung Kao ,  Chia-Pin Cheng ,  Kuo-Cheng Lee ,  Hsun-Ying Huang ,  Yen-Liang Lin

IPC: H01L27/146 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US20240387380A1

公开(公告)日：2024-11-21

申请号：US18785281

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chun Wang ,  Tzy-Kuang Lee ,  Chih-Hsien Lin ,  Ching-Hung Kao ,  Yen-Yu Chen

IPC: H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.