公开(公告)号：US20220165847A1

公开(公告)日：2022-05-26

申请号：US17650867

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Miao-Syuan FAN ,  Pei-Wei LEE ,  Ching-Hua LEE ,  Jung-Wei LEE

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US20210234000A1

公开(公告)日：2021-07-29

申请号：US16937365

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Miao-Syuan FAN ,  Pei-Wei LEE ,  Ching-Hua LEE ,  Jung-Wei LEE

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8234

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US20210082707A1

公开(公告)日：2021-03-18

申请号：US16573596

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Miao-Syuan FAN ,  Ching-Hua LEE ,  Ming-Te CHEN ,  Jung-Wei LEE ,  Pei-Wei LEE

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

公开(公告)号：US20240234506A1

公开(公告)日：2024-07-11

申请号：US18612701

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Miao-Syuan FAN ,  Pei-Wei LEE ,  Ching-Hua LEE ,  Jung-Wei LEE

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US20180374754A1

公开(公告)日：2018-12-27

申请号：US15724650

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua LEE ,  Jung-Wei LEE ,  Wen-Chieh HUANG

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06

Abstract: A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals, wherein the nitrogen-based radicals are distributed along a sidewall and over a top surface of the upper portion of the fin with respective different concentrations; and forming an oxide layer over the upper portion of the fin using a thermal oxidation process.

公开(公告)号：US20150221515A1

公开(公告)日：2015-08-06

申请号：US14170837

申请日：2014-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yuan HO ,  Jung-Wei LEE ,  Ming-Te CHEN

IPC: H01L21/265 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L21/26593 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67745

Abstract: Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer.

Abstract translation: 提供了在离子注入工艺中冷却晶片的方法的实施例。 用于在离子注入工艺中冷却晶片的方法包括将晶片放置在处理模块中。 该方法还包括在晶片上执行离子注入工艺并同时冷却处理模块中的晶片。 该方法还包括从处理模块移除晶片。 此外，该方法包括加热晶片。