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公开(公告)号:US11906897B2
公开(公告)日:2024-02-20
申请号:US17350685
申请日:2021-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
CPC classification number: G03F1/24 , G03F1/26 , G03F1/80 , G03F1/84 , G03F7/70433 , G03F7/70466 , H01L21/2633
Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.
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公开(公告)号:US11119398B2
公开(公告)日:2021-09-14
申请号:US16383570
申请日:2019-04-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hsin-Chang Lee , Pei-Cheng Hsu , Ping-Hsun Lin , Ta-Cheng Lien , Tzu Yi Wang
IPC: G03F1/22 , H01L21/027
Abstract: A photo mask for extreme ultra violet (EUV) lithography includes a substrate having a front surface and a back surface opposite to the front surface, a multilayer Mo/Si stack disposed on the front surface of the substrate, a capping layer disposed on the multilayer Mo/Si stack, an absorber layer disposed on the capping layer, and a backside conductive layer disposed on the back surface of the substrate. The backside conductive layer is made of tantalum boride.
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公开(公告)号:US20190324364A1
公开(公告)日:2019-10-24
申请号:US15956189
申请日:2018-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
Abstract: A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.
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公开(公告)号:US11249384B2
公开(公告)日:2022-02-15
申请号:US16441700
申请日:2019-06-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng Hsu , Chi-Ping Wen , Tzu Yi Wang , Ta-Cheng Lien , Hsin-Chang Lee
IPC: G03F1/22
Abstract: A method of manufacturing an extreme ultraviolet (EUV) lithography mask includes forming an image pattern in an absorption layer of EUV mask blank. The EUV mask blank includes: a multilayer stack including alternating molybdenum (Mo) and silicon (Si) layers disposed over a first surface of a mask substrate, a capping layer disposed over the multilayer stack, and an absorption layer disposed over the capping layer. A border region surrounds the image pattern having a trench wherein the absorption layer, the capping layer and at least a portion of the multilayer stack are etched. Concave sidewalls are formed in the border region or an inter-diffused portion is formed in the multilayer stack of the trench.
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公开(公告)号:US20210311383A1
公开(公告)日:2021-10-07
申请号:US17350685
申请日:2021-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.
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公开(公告)号:US11237477B2
公开(公告)日:2022-02-01
申请号:US16012253
申请日:2018-06-19
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng Hsu , Ta-Cheng Lien , Tzu Yi Wang , Hsin-Chang Lee
IPC: G03F1/66 , G03F7/20 , H01L21/673
Abstract: A mask container for storing a mask for photolithography, includes a cover and a base having a plurality of tapered corners. The tapered corners taper outward and downward from a top major surface of the base. The cover having the tapered corners extends downward that covers the tapered corners of the base when the cover is attached to the base. The tapered corners of the cover are tapered at about the same angle as the tapered corners of the base so that a surface of the tapered corners of the cover is substantially parallel to a corresponding surface of the tapered corner of the base when the cover is attached to the base. A recess is located in the tapered corners of the cover. A biasing member and a ball-shaped member are located in the tapered corners of the base to mate with the recess when the cover is attached to the base.
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公开(公告)号:US11106126B2
公开(公告)日:2021-08-31
申请号:US16383535
申请日:2019-04-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hsin-Chang Lee , Pei-Cheng Hsu , Ta-Cheng Lien , Tzu Yi Wang
Abstract: In a method of manufacturing a photo mask, an etching mask layer having circuit patterns is formed over a target layer of the photo mask to be etched. The photo mask includes a backside conductive layer. The target layer is etched by plasma etching, while preventing active species of plasma from attacking the backside conductive layer.
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公开(公告)号:US11048158B2
公开(公告)日:2021-06-29
申请号:US15956189
申请日:2018-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
Abstract: A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.
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