公开(公告)号：US20220359512A1

公开(公告)日：2022-11-10

申请号：US17875060

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20170309562A1

公开(公告)日：2017-10-26

申请号：US15135493

申请日：2016-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Li-Chun TIEN ,  Pin-Dai SUE

IPC: H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US20210098453A1

公开(公告)日：2021-04-01

申请号：US17120839

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20170323877A1

公开(公告)日：2017-11-09

申请号：US15145354

申请日：2016-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US20240021613A1

公开(公告)日：2024-01-18

申请号：US18362755

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Dai SUE ,  Tzung-Yo HUNG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L23/528 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/66545 ,  H01L21/823437

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.

公开(公告)号：US20180006009A1

公开(公告)日：2018-01-04

申请号：US15201200

申请日：2016-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/12 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L2027/11875

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US20150031194A1

公开(公告)日：2015-01-29

申请号：US14511932

申请日：2014-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hang YANG ,  Chun-Fu CHEN ,  Pin-Dai SUE ,  Hui-Zhong ZHUANG

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/60 ,  H01L21/283

CPC classification number: H01L21/28008 ,  H01L21/283 ,  H01L21/76895 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

Abstract translation: 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。