公开(公告)号：US12217936B2

公开(公告)日：2025-02-04

申请号：US18504415

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01L21/02 ,  H01J37/32 ,  H01L21/311 ,  H01L21/321

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US11855153B2

公开(公告)日：2023-12-26

申请号：US17245766

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Chia-Yang Hung ,  Sheng-Liang Pan

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522 ,  H01L29/45 ,  H01L21/3215 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/31122 ,  H01L21/76805 ,  H01L21/76859 ,  H01L21/76877 ,  H01L21/3215 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/41791 ,  H01L29/456

Abstract: A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.

公开(公告)号：US11854766B2

公开(公告)日：2023-12-26

申请号：US17869557

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01L21/321 ,  H01L21/311 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32027 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/0212 ,  H01L21/02063 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31138 ,  H01L21/321 ,  H01J2237/3341

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US12205816B2

公开(公告)日：2025-01-21

申请号：US17232465

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

公开(公告)号：US20230268223A1

公开(公告)日：2023-08-24

申请号：US17652398

申请日：2022-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L23/53257 ,  H01L23/535

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.

公开(公告)号：US20230178361A1

公开(公告)日：2023-06-08

申请号：US17720033

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Hung ,  Huan-Just Lin ,  Sheng-Liang Pan ,  Yungtzu Chen ,  Po-Chuan Wang ,  Guan-Xuan Chen

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02052 ,  H01L21/02315 ,  H01L21/823418 ,  H01L21/823431

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

公开(公告)号：US20220359158A1

公开(公告)日：2022-11-10

申请号：US17869557

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/321 ,  H01L21/311

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US20220102138A1

公开(公告)日：2022-03-31

申请号：US17232465

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

公开(公告)号：US20200020541A1

公开(公告)日：2020-01-16

申请号：US16035819

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pang-Sheng Chang ,  Yu-Feng Yin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao ,  Chia-Yang Hung ,  Chia-Sheng Chang ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Sheng-Liang Pan ,  Jack Kuo-Ping Kuo ,  Shao-Jyun Wu

IPC: H01L21/321 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

公开(公告)号：US12293910B2

公开(公告)日：2025-05-06

申请号：US18359552

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.