公开(公告)号：US20210341961A1

公开(公告)日：2021-11-04

申请号：US17375054

申请日：2021-07-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshitada SAITO ,  Akihisa FUJIMOTO

IPC: G06F1/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/07 ,  H03L7/091 ,  H03L7/00 ,  H04L25/08 ,  H04L25/14 ,  G06F1/12 ,  G06F13/38 ,  G06F13/42 ,  H03L7/08 ,  H03L7/099

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US20190286334A1

公开(公告)日：2019-09-19

申请号：US16429388

申请日：2019-06-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akihisa FUJIMOTO

IPC: G06F3/06 ,  G06F13/42 ,  G06F12/02

Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

公开(公告)号：US20210191621A1

公开(公告)日：2021-06-24

申请号：US17196390

申请日：2021-03-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akihisa FUJIMOTO

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42

Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

公开(公告)号：US20190243410A1

公开(公告)日：2019-08-08

申请号：US16389340

申请日：2019-04-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshitada SAITO ,  Akihisa FUJIMOTO

IPC: G06F1/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00 ,  G06F13/42

CPC classification number: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/4282 ,  H03L7/00 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/099 ,  H04L7/0004 ,  H04L7/0012 ,  H04L7/033 ,  H04L25/085 ,  H04L25/14

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US20200333874A1

公开(公告)日：2020-10-22

申请号：US16917043

申请日：2020-06-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akihisa FUJIMOTO

IPC: G06F1/3296 ,  G06F13/40 ,  G06F1/3228 ,  G06F1/3234 ,  G06F3/06 ,  G06K7/00 ,  G06K19/077 ,  G06F12/02

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

公开(公告)号：US20200004318A1

公开(公告)日：2020-01-02

申请号：US16564441

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akihisa FUJIMOTO

IPC: G06F1/3296 ,  G06F13/40 ,  G06F1/3228 ,  G06F1/3234 ,  G06F3/06 ,  G06K7/00 ,  G06K19/077 ,  G06F12/02

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

公开(公告)号：US20180232155A1

公开(公告)日：2018-08-16

申请号：US15955867

申请日：2018-04-18

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akihisa FUJIMOTO

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/4234 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/177 ,  G06F2212/7202

Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

公开(公告)号：US20200035289A1

公开(公告)日：2020-01-30

申请号：US16084094

申请日：2017-03-15

Applicant: Toshiba Memory Corporation

Inventor： Akihisa FUJIMOTO

IPC: G11C11/4074 ,  G11C11/409 ,  G11C7/22 ,  G11C29/50 ,  G11C29/02

Abstract: A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.