公开(公告)号：US10090833B2

公开(公告)日：2018-10-02

申请号：US15608436

申请日：2017-05-30

Applicant: Texas Instruments Incorporated

Inventor： Vinod Menezes

IPC: H03L7/00 ,  H03K17/22 ,  H03K5/04 ,  H03K5/24

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.

公开(公告)号：US20180005693A1

公开(公告)日：2018-01-04

申请号：US15706901

申请日：2017-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vinod Menezes

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C11/412 ,  G11C11/413

Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.

公开(公告)号：US20250167779A1

公开(公告)日：2025-05-22

申请号：US18950397

申请日：2024-11-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Divya Kaur ,  Vinod Menezes ,  Rajat Chauhan

IPC: H03K17/14

Abstract: Some aspects relate to a circuit comprising a temperature-dependent circuit, a proportional to absolute temperature (PTAT) current sink, a complementary to absolute temperature current source (CTAT) current source, and a heating element. The temperature-dependent circuit is disposed within an integrated circuit package. The PTAT current sink is disposed within the integrated circuit package and has an output terminal. The CTAT current source is disposed within the integrated circuit package and has an output terminal coupled to the output terminal of the PTAT current sink. The heating element is disposed within the integrated circuit package and has a control terminal coupled to the output terminal of the PTAT current sink and the output terminal of the CTAT current source.

公开(公告)号：US20210234456A1

公开(公告)日：2021-07-29

申请号：US17228618

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishalay Datta ,  Vinod Menezes

IPC: H02M1/08 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/30 ,  H02M3/00

Abstract: In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.

公开(公告)号：US20180190343A1

公开(公告)日：2018-07-05

申请号：US15393552

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Vinod Menezes

IPC: G11C11/417 ,  G11C11/412

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/412

Abstract: A memory array and an integrated circuit are disclosed. The memory array includes first and second banks of memory elements and five switches. Each memory element of the first bank of memory elements is coupled to an upper rail and to a first node, while each memory element of the second bank of memory elements is coupled to a second node and to a lower rail. The first switch is coupled between the first node and the second node; the second switch is coupled between the first node and the lower rail; and the third switch is coupled between the second node and the upper rail. A fourth switch is coupled between the first node and a voltage that is one diode drop above the lower rail, and a fifth switch is coupled between the second node and a voltage that is one diode drop below the upper rail.

公开(公告)号：US09741430B2

公开(公告)日：2017-08-22

申请号：US15284890

申请日：2016-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vinod Menezes

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418

Abstract: A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.

公开(公告)号：US20160314832A1

公开(公告)日：2016-10-27

申请号：US15199167

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

Abstract translation: 在所述示例中，存储器控制器电路控制对SRAM电路的访问。 预充电模式控制电路输出：到SRAM电路的突发模式使能信号，指示将沿着选定的一行SRAM单元的一系列SRAM单元被访问; 向SRAM电路提供预充电第一模式信号，指示将发生沿着所选行的第一次访问; 以及向SRAM电路提供预充电最后模式信号，指示将发生沿着所选行的最后访问。 SRAM电路包括以行和列排列以存储数据的SRAM单元的阵列。 每个SRAM单元耦合到：沿着一行SRAM单元的相应字线; 和相应的一对互补位线。

公开(公告)号：US20230062353A1

公开(公告)日：2023-03-02

申请号：US17733714

申请日：2022-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Divya Kaur ,  Muthusubramanian N. Venkateswaran ,  Vinod Menezes

IPC: H03K19/0185

Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.

公开(公告)号：US20200379031A1

公开(公告)日：2020-12-03

申请号：US16901966

申请日：2020-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

公开(公告)号：US20170294910A1

公开(公告)日：2017-10-12

申请号：US15608436

申请日：2017-05-30

Applicant: Texas Instruments Incorporated

Inventor： Vinod Menezes

IPC: H03K17/22 ,  H03K5/24 ,  H03K5/04

CPC classification number: H03K17/223 ,  H03K5/04 ,  H03K5/2472

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.