公开(公告)号：US20240072756A1

公开(公告)日：2024-02-29

申请号：US17900599

申请日：2022-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shaoping TANG ,  Keegan MARTIN ,  Ting-Ta YEN

IPC: H03H9/02 ,  H03H9/17

CPC classification number: H03H9/02015 ,  H03H9/171

Abstract: A BAW resonator includes first and second electrodes located over a substrate. A piezoelectric layer is located between the first and second electrodes. A guard ring is located between the piezoelectric layer and the second electrode, and is spaced apart from a perimeter of the electrode. The guard ring has a width in a range from 2.5 μm to 3.5 μm.

公开(公告)号：US20150187938A1

公开(公告)日：2015-07-02

申请号：US14576693

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Shaoping TANG ,  Amitava CHATTERJEE ,  Imran Mahmood KHAN ,  Kaiping LIU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其在DEMOS栅极下具有较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US20160035890A1

公开(公告)日：2016-02-04

申请号：US14885637

申请日：2015-10-16

Applicant: Texas Instruments Incorporated

Inventor： Shaoping TANG ,  Amitava CHATTERJEE ,  Imran Mahmood KHAN ,  Kaiping LIU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.