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公开(公告)号：US10763664B2
公开(公告)日：2020-09-01
申请号：US16132790
申请日：2018-09-17
Applicant: Texas Instruments Incorporated
Inventor： Ricky Dale Jordanger , Hector Torres
IPC: H02H9/00 , H02H9/02 , H03K17/687
Abstract: A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short
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公开(公告)号：US20230274989A1
公开(公告)日：2023-08-31
申请号：US17683308
申请日：2022-02-28
Applicant: Texas Instruments Incorporated
Inventor： Ramlah Binte Abdul Razak , Hector Torres
IPC: H01L23/047 , H01L23/367 , H01L21/48
CPC classification number: H01L23/047 , H01L23/367 , H01L21/4807 , H01L21/4817
Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.
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公开(公告)号：US10651844B2
公开(公告)日：2020-05-12
申请号：US16190871
申请日：2018-11-14
Applicant: Texas Instruments Incorporated
Inventor： Lawrence James Gewax , Kevin William Ziemer , Ricky Dale Jordanger , Hector Torres
IPC: H03L7/00 , H03K17/687 , G01R19/165
Abstract: An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.
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公开(公告)号：US20200043825A1
公开(公告)日：2020-02-06
申请号：US16267907
申请日：2019-02-05
Applicant: Texas Instruments Incorporated
IPC: H01L23/367 , H01L23/498 , H01L23/00 , H01L21/48
Abstract: A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.
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公开(公告)号：US09793707B2
公开(公告)日：2017-10-17
申请号：US13903736
申请日：2013-05-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hector Torres , Charles Parkhurst
CPC classification number: H02H9/02 , G05F1/5735 , G05F1/575 , H02H9/001
Abstract: Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter includes two current sense element/current clamp control loops. A fast response time control loop first engages and clamps a current spike. A precision control loop then engages to more accurately clamp the output current to a programmed set point. The precision clamping loop includes an inner loop to linearize the precision current sense element. The inner loop forces the drain-to-source voltage (VDS) of the precision sense element to track the VDS of the regulator pass element. A more precise clamping operation results. Overall speed is not sacrificed as the fast response time clamping loop operates in parallel to protect circuitry while the precision clamping loop engages.
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Patent Agency Ranking
公开(公告)号：US09571051B2
公开(公告)日：2017-02-14
申请号：US14674220
申请日：2015-03-31
Applicant: Texas Instruments Incorporated
Inventor： Charles Parkhurst , Hector Torres
CPC classification number: H03F3/45928 , H03F3/45179 , H03F3/45475 , H03F3/45632 , H03F2200/261 , H03F2203/45116 , H03F2203/45522 , H03F2203/45528
Abstract: An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.
Abstract translation: 一种仪表放大器（INA），包括耦合到第一放大器的第一放大器和第二放大器。 第一放大器包括第一晶体管。 第一放大器被配置为接收差分信号的正相位信号。 第二放大器包括第二晶体管，并且被配置为接收差分信号的负相位信号。 第一和第二晶体管各自包括栅极，源极和漏极。 第一晶体管漏极连接到第二晶体管漏极。
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公开(公告)号：US11915986B2
公开(公告)日：2024-02-27
申请号：US17683308
申请日：2022-02-28
Applicant: Texas Instruments Incorporated
Inventor： Ramlah Binte Abdul Razak , Hector Torres
IPC: H01L23/047 , H01L23/367 , H01L21/48
CPC classification number: H01L23/047 , H01L21/4807 , H01L21/4817 , H01L23/367
Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.
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公开(公告)号：US11088047B2
公开(公告)日：2021-08-10
申请号：US16267907
申请日：2019-02-05
Applicant: Texas Instruments Incorporated
IPC: H01L23/367 , H01L23/498 , H01L23/00 , H01L21/48
Abstract: A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.
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9.发明申请公开(公告)号：US20190386657A1
公开(公告)日：2019-12-19
申请号：US16190871
申请日：2018-11-14
Applicant: Texas Instruments Incorporated
Inventor： Lawrence James Gewax , Kevin William Ziemer , Ricky Dale Jordanger , Hector Torres
IPC: H03K17/687 , H03L7/00 , G01R19/165
Abstract: An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.
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公开(公告)号：US11218123B2
公开(公告)日：2022-01-04
申请号：US16817084
申请日：2020-03-12
Applicant: Texas Instruments Incorporated
Inventor： Ricky Dale Jordanger , Hector Torres
Abstract: A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.
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