公开(公告)号：US20240334609A1

公开(公告)日：2024-10-03

申请号：US18609434

申请日：2024-03-19

Applicant: TDK Corporation

Inventor： Toshiyuki ABE ,  Kazutoshi TSUYUTANI ,  Naoyuki ISHIKAWA

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/182 ,  H05K1/0237 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/10439

Abstract: Disclosed herein is an apparatus that includes a multilayer substrate including a plurality of conductive layers and a plurality of insulating layers alternately stacked, and an electronic component having a first signal pad. The plurality of conductive layers include a first internal conductive layer having a first signal pattern, and a second internal conductive layer having a second signal pattern. The plurality of insulating layers include a first insulating layer positioned between the first and second internal conductive layers. The electronic component is embedded in the first insulating layer such that the first signal pad is connected to the first signal pattern. The first and second signal patterns are connected to each other by a first via conductor penetrating through the first insulating layer. The distance between the electronic component and the first via conductor is greater than a diameter of the first via conductor.

公开(公告)号：US20240155765A1

公开(公告)日：2024-05-09

申请号：US18549263

申请日：2022-02-22

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI ,  Naoyuki ISHIKAWA ,  Takuro AOKI ,  Reo HANADA

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/03 ,  H05K1/0298 ,  H05K1/182 ,  H05K3/46

Abstract: To enhance the degree of design freedom of an outermost conductor layer in an electronic component embedded substrate. An electronic component embedded substrate includes conductor layers, insulating layers each of which is positioned between adjacent two of the conductor layers, and an electronic component embedded in the insulating layer. The conductor layer is positioned in the uppermost layer and includes a plurality of terminal electrodes exposed to one surface side. The insulating layers are each made of a core material obtained by impregnating a core with a resin material, while the insulating layers are made of a resin material not containing a core. Since the insulating layer is made of a resin material not containing a core, the diameter of a via conductor formed in the insulating layer can be reduced. Thus, even when the plurality of terminal electrodes are formed in the conductor layer with a small pitch, the routing distance of wires can be reduced.

公开(公告)号：US20200161199A1

公开(公告)日：2020-05-21

申请号：US16550995

申请日：2019-08-26

Applicant: TDK CORPORATION

Inventor： Kazutoshi TSUYUTANI ,  Yoshihiro SUZUKI ,  Akira MOTOHASHI

IPC: H01L23/13 ,  H01L25/18 ,  H01L23/538 ,  G01L9/00 ,  G01H3/00 ,  G01K13/02 ,  G01N33/00

Abstract: A sensor package substrate disclosed in the present specification has a mounting area in which a sensor chip is mounted and a controller chip connected to the sensor chip. A through hole is formed in the sensor package substrate so as to overlap the mounting area in a plan view and to penetrate the substrate from one surface to the other surface thereof. The mounting area and the controller chip overlap each other in a plan view. According to the present invention, by reducing the thickness of an insulating layer, it is possible not only to reduce the distance of a wiring for the sensor chip and controller chip, but also to reduce the area of the substrate.

公开(公告)号：US20140104803A1

公开(公告)日：2014-04-17

申请号：US14054556

申请日：2013-10-15

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/42

CPC classification number: H05K1/185 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2924/15313 ,  H05K1/115 ,  H05K3/30 ,  H05K3/42 ,  H05K2201/09727 ,  H05K2201/09854 ,  H05K2203/1469 ,  Y10T29/49146

Abstract: Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.

Abstract translation: 这里公开了一种电路板，其包括具有基板布线层的树脂基板和嵌入树脂基板中并具有多个外部电极的电子部件。 树脂基板具有使外部电极露出的多个通孔以及埋设在通路孔中的多个通路导体，将基板布线层与外部电极电连接。 至少一些通孔在平面形状上彼此不同。

公开(公告)号：US20240014112A1

公开(公告)日：2024-01-11

申请号：US18249862

申请日：2021-10-22

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI ,  Tadashi MITO ,  Eisuke YONEKURA ,  Michitaka OKAZAKI ,  Masumi KAMEDA

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/142 ,  H01L21/4857

Abstract: An electronic component embedded substrate includes conductor layers L1 to L3, insulating layers 112 and 113 provided between the conductor layers L2 and L3, an insulating layer 114 provided between the conductor layers L1 and L2, a semiconductor embedded in the insulating layers 112 and 113, a via conductor 142 filling a via V, and a via conductor 143 filling a via 143a. The via 143a is provided at such a position that overlaps the via V and is shallower than the via V. The inner wall of the via 143a is larger in surface roughness than the inner wall of the via V. This makes voids less likely to occur in the via conductor 142 filling the deep via V and enhances adhesion between the via conductor 143 and the shallow via 143a that the via conductor 143 fills.

公开(公告)号：US20150145145A1

公开(公告)日：2015-05-28

申请号：US14555325

申请日：2014-11-26

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI ,  Masashi KATSUMATA

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4918 ,  H01L2224/83132 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.

Abstract translation: 这里公开了一种IC嵌入式基板，其包括具有开口的芯基板，设置在开口中的IC芯片，下绝缘层和上绝缘层。 IC芯片和芯基板夹在下绝缘层和上绝缘层之间。 上绝缘层以填充IC芯片的侧表面和芯基板的开口的内周表面之间的间隙的方式形成。 从IC芯片的上表面到上绝缘层的上表面的第一距离短于从芯基板的上表面到上绝缘层的上表面的第二距离。

公开(公告)号：US20240364291A1

公开(公告)日：2024-10-31

申请号：US18641783

申请日：2024-04-22

Applicant: TDK Corporation

Inventor： Toshiyuki ABE ,  Ichiro YAGINUMA ,  Kazutoshi TSUYUTANI ,  Takuya SHIMAMURA

IPC: H03H7/01 ,  H01R12/58 ,  H01R12/75 ,  H01R13/66 ,  H01R13/7197 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18

CPC classification number: H03H7/01 ,  H01R13/7197 ,  H05K1/117 ,  H05K1/165 ,  H05K1/185 ,  H01R12/58 ,  H01R12/75 ,  H01R13/6666 ,  H05K2201/09181 ,  H05K2201/10174 ,  H05K2201/10189

Abstract: Disclosed herein is a circuit board that includes: a plurality of insulating layers, a common mode filter and an electronic component embedded in the insulating layers, and first to fifth outer electrodes. The first coil pattern of the common mode filter is connected between the first and second outer electrodes. The second coil pattern of the common mode filter is connected between the third and fourth outer electrodes. The electronic component is connected between the first and second outer electrodes and the fifth outer electrode. The electronic component is arranged so as not to overlap the first coil pattern and the second coil pattern.

公开(公告)号：US20220406670A1

公开(公告)日：2022-12-22

申请号：US17894584

申请日：2022-08-24

Applicant: TDK CORPORATION

Inventor： Kazutoshi TSUYUTANI ,  Yoshihiro SUZUKI ,  Akira MOTOHASHI

IPC: H01L23/13 ,  H01L25/18 ,  H01L23/538 ,  G01H3/00 ,  G01K13/02 ,  G01N33/00 ,  G01L9/00

Abstract: A sensor package substrate disclosed in the present specification has a mounting area in which a sensor chip is mounted and a controller chip connected to the sensor chip. A through hole is formed in the sensor package substrate so as to overlap the mounting area in a plan view and to penetrate the substrate from one surface to the other surface thereof. The mounting area and the controller chip overlap each other in a plan view. According to the present invention, by reducing the thickness of an insulating layer, it is possible not only to reduce the distance of a wiring for the sensor chip and controller chip, but also to reduce the area of the substrate.

公开(公告)号：US20220267142A1

公开(公告)日：2022-08-25

申请号：US17620485

申请日：2020-06-05

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI ,  Yoshihiro SUZUKI

IPC: B81B7/00 ,  B81C1/00 ,  G01D11/24

Abstract: A sensor package substrate has through holes V1 and V2 at a position overlapping a sensor chip mounting area. The through hole V1 has a minimum inner diameter at a depth position D1, and the through hole V2 has a minimum inner diameter at a depth position D2 different from the depth position D1. Thus, since the plurality of through holes are formed at a position overlapping the sensor chip mounting area, the diameter of each of the through holes can be reduced. This makes foreign matters unlikely to enter through the through holes, and a reduction in the strength of the substrate is suppressed. In addition, since the depth position D1 and depth position D2 are located at different depth levels, it is possible to sufficiently maintain the strength of a part of the substrate that is positioned between the through holes V1 and V2.

公开(公告)号：US20140085854A1

公开(公告)日：2014-03-27

申请号：US14032093

申请日：2013-09-19

Applicant: TDK Corporation

Inventor： Kazutoshi TSUYUTANI ,  Hiroshige Ohkawa ,  Yoshihiro Suzuki ,  Tsuyoshi Mochizuki

IPC: H05K1/03 ,  H05K3/30

CPC classification number: H05K1/03 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49572 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/188 ,  H05K3/007 ,  H05K3/305 ,  H05K2201/068 ,  H05K2203/0152 ,  Y10T29/4913

Abstract: Disclosed herein is a manufacturing method of a circuit board. The manufacturing method includes a first step for preparing a prepreg in which a core material is impregnated with an uncured resin. The prepreg has a through-hole surrounded by the core material and the resin so as to penetrate through the core material and the resin. The manufacturing method further includes a second step for housing a semiconductor IC in the through-hole, and a third step for pressing the prepreg so that a part of the resin flows into the through-hole to allow the semiconductor IC housed in the through-hole to be embedded in the resin.

Abstract translation: 这里公开了电路板的制造方法。 制造方法包括：制备预浸料坯的第一步骤，其中芯材浸渍有未固化的树脂。 预浸料坯具有被芯材和树脂包围的贯通孔，从而贯穿芯材和树脂。 该制造方法还包括用于在通孔中容纳半导体IC的第二步骤，以及第三步骤，用于对预浸料坯进行挤压，使得一部分树脂流入通孔以允许容纳在通孔中的半导体IC， 要嵌入树脂中的孔。