公开(公告)号：US20180151363A1

公开(公告)日：2018-05-31

申请号：US15867052

申请日：2018-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.

公开(公告)号：US09530728B2

公开(公告)日：2016-12-27

申请号：US14845977

申请日：2015-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Jen Sung ,  Yi-Nien Su

IPC分类号： H01L21/76 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L22/26 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.

公开(公告)号：US09041216B2

公开(公告)日：2015-05-26

申请号：US13922051

申请日：2013-06-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Jen Sung ,  Yi-Nien Su

IPC分类号： H01L29/40 ,  H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/7681 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括下部低k（LK）电介质层中的较低导电特征; 在所述下导电特征上的第一蚀刻停止层（ESL），其中所述第一ESL包括金属化合物; 第一ESL上的上LK电介质层; 以及上部LK介电层中的上部导电特征，其中上部导电特征延伸穿过第一ESL并连接到下部导电特征。 互连结构还可以包括在上LK介电层和第一ESL之间或第一ESL与下导电特征之间的第二ESL，其中第二ESL包括硅化合物。

公开(公告)号：US20220384243A1

公开(公告)日：2022-12-01

申请号：US17884714

申请日：2022-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su ,  Jyu-Horng Shieh

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/522

摘要： Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

公开(公告)号：US20190237333A1

公开(公告)日：2019-08-01

申请号：US16378340

申请日：2019-04-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.

公开(公告)号：US10276381B2

公开(公告)日：2019-04-30

申请号：US15867052

申请日：2018-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768

摘要： In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.

公开(公告)号：US09881794B1

公开(公告)日：2018-01-30

申请号：US15363928

申请日：2016-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

摘要： In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.

公开(公告)号：US20140264895A1

公开(公告)日：2014-09-18

申请号：US13890148

申请日：2013-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Su-Jen Sung ,  Yi-Nien Su

IPC分类号： H01L21/311 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L22/26 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.

摘要翻译： 公开了半导体器件及其制造方法。 在一些实施例中，制造半导体器件的方法包括在工件上形成蚀刻停止层。 蚀刻停止层对工件的材料层具有大于约4至约30的蚀刻选择性。该方法包括在蚀刻停止层上形成绝缘材料层，并使用蚀刻停止层将绝缘材料层图案化为 蚀刻停止。

公开(公告)号：US20230360966A1

公开(公告)日：2023-11-09

申请号：US18356911

申请日：2023-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su ,  Jyu-Horng Shieh

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L23/535 ,  H01L23/53252 ,  H01L21/76895 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53257 ,  H01L23/5226

摘要： Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

公开(公告)号：US11710657B2

公开(公告)日：2023-07-25

申请号：US17147177

申请日：2021-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su ,  Jyu-Horng Shieh

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/5329 ,  H01L23/53252 ,  H01L23/53257

摘要： Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.