知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.021 秒)

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING SIMULATION SAMPLE
    5.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING SIMULATION SAMPLE 审中-公开
    用于生成模拟样本的方法，系统和计算机程序产品

    公开(公告)号：US20160055273A1

    公开(公告)日：2016-02-25

    申请号：US14464464

    申请日：2014-08-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chin-Cheng KUO ,  Wei Min CHAN ,  Wei-Yu HU ,  Jui-Feng KUAN

    IPC分类号： G06F17/50 ,  G06F11/30 ,  G06F11/34

    CPC分类号： G06F17/5009 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3457 ,  G06F17/5081 ,  G06F2217/10

    摘要： A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

    摘要翻译： 一种方法包括确定样本空间中的采样区域，在采样区域内生成样本，而不在采样区域之外生成样本，以及使用生成的采样作为输入数据来模拟设备的性能。 样本空间由与设备相关联的多个变量定义。 采样区域中的多个变量的值比采样区域外的多个变量的值更低，以满足器件的规格。 该方法至少部分地由至少一个处理器执行。

    STATIC RANDOM ACCESS MEMORY AND METHOD OF USING THE SAME
    6.
    发明申请
    STATIC RANDOM ACCESS MEMORY AND METHOD OF USING THE SAME 有权
    静态随机访问存储器及其使用方法

    公开(公告)号：US20150371702A1

    公开(公告)日：2015-12-24

    申请号：US14308065

    申请日：2014-06-18

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Wei-Cheng WU ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Ping-Wei WANG

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

    摘要： A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.

    摘要翻译： 一种包括位单元的静态随机存取存储器（SRAM），其中所述位单元包括至少两个p型通道门。 SRAM还包括连接到位单元的位线和连接到位单元的位线条。 SRAM还包括连接到位线和位线条的预放电电路，其中预放电电路包括至少两个n型晶体管。 SRAM还包括连接到位线和位线条的交叉耦合晶体管，其中交叉耦合晶体管的每个晶体管是n型晶体管。 SRAM还包括连接到位线和位线条的写入多路复用器，其中写入多路复用器包括两个p型晶体管。

    MEMORY DEVICE, METHOD, LAYOUT, AND SYSTEM
    8.
    发明公开
    MEMORY DEVICE, METHOD, LAYOUT, AND SYSTEM 审中-公开

    公开(公告)号：US20240251541A1

    公开(公告)日：2024-07-25

    申请号：US18325861

    申请日：2023-05-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen Lin CHUNG ,  Kao-Cheng LIN ,  Wei Min CHAN ,  Yen-Huei CHEN

    IPC分类号： H10B10/00 ,  G06F30/392 ,  G11C11/419

    CPC分类号： H10B10/18 ,  G06F30/392 ,  G11C11/419

    摘要： A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.