公开(公告)号：US10056472B2

公开(公告)日：2018-08-21

申请号：US15152205

申请日：2016-05-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L21/3213 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/66795 ,  B82Y10/00 ,  H01L21/32134 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785

摘要： A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H2SO4, HCl, HF, H3PO4, or NH4OH and (b) a second component, including propylene carbonate, ethylene carbonate, diethyl carbonate, acetonitrile, or a combination thereof.

公开(公告)号：US20220157956A1

公开(公告)日：2022-05-19

申请号：US17097468

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Hsiu Chen ,  Andrew Joseph Kelly

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

公开(公告)号：US11145544B2

公开(公告)日：2021-10-12

申请号：US16407951

申请日：2019-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Andrew Joseph Kelly

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L21/285 ,  C23F1/10

摘要： The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid.

公开(公告)号：US10854736B2

公开(公告)日：2020-12-01

申请号：US16105830

申请日：2018-08-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3213 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/45

摘要： Methods for manufacturing semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer by using an etching solvent. In addition, the etching solvent includes (a) a first component and (b) a second component. The first component includes an acid, and the second component includes propylene carbonate (PC), ethylene carbonate (EC), diethyl carbonate (DEC), or a combination thereof.

公开(公告)号：US10720344B2

公开(公告)日：2020-07-21

申请号：US16673777

申请日：2019-11-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/3063 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  B82Y10/00 ,  C25F3/12 ,  H01L29/417 ,  C25F7/00 ,  H01L29/775 ,  H01L29/786 ,  H01L29/78 ,  C25D17/00 ,  H01L29/06 ,  H01L29/51

摘要： A method includes forming a semiconductor fin on a semiconductor substrate, the semiconductor fin comprising germanium, silicon, silicon germanium or any of III-V elements; forming a mask layer on a top portion of the semiconductor fin; and trimming the semiconductor fin, wherein trimming the semiconductor fin comprises: immersing the semiconductor substrate in a first electrolyte bath; and laterally removing a first portion of the semiconductor fin by supplying a first voltage to a counter electrode in the electrolyte bath and a second voltage to the semiconductor substrate, wherein the second voltage is negative.

公开(公告)号：US09385197B2

公开(公告)日：2016-07-05

申请号：US14525888

申请日：2014-10-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L21/465 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66795 ,  B82Y10/00 ,  H01L21/32134 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785

摘要： A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H2SO4, HCl, HF, H3PO4, or NH4OH and (b) a second component, including propylene carbonate, ethylene carbonate, diethyl carbonate, acetonitrile, or a combination thereof.

摘要翻译： 提供半导体结构及其形成方法。 该方法包括在衬底中形成源极/漏极结构并在源极/漏极结构上形成金属层。 制造半导体结构的方法还包括进行退火处理，使得金属层的一部分与源极/漏极结构反应以在源极/漏极结构上形成金属层。 制造半导体结构的方法还包括进行蚀刻工艺以除去金属层上的金属层的未反应部分并在金属层上形成接触。 此外，蚀刻工艺包括使用蚀刻溶剂，并且蚀刻溶剂包括（a）第一组分，包括H 2 SO 4，HCl，HF，H 3 PO 4或NH 4 OH和（b）第二组分，包括碳酸亚丙酯，碳酸亚乙酯， 碳酸二乙酯，乙腈或其组合。

公开(公告)号：US09324820B1

公开(公告)日：2016-04-26

申请号：US14608805

申请日：2015-01-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/324 ,  H01L21/306 ,  H01L21/283 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/8234

CPC分类号： H01L29/41783 ,  H01L21/32134 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823443 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/66795

摘要： A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes removing an unreacted portion of the metal layer on the metallic layer by an etching process. In addition, the etching process includes using an etchant including HF and propylene carbonate, and the volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:10 to about 1:10000.

摘要翻译： 提供半导体结构及其形成方法。 制造半导体结构的方法包括在衬底上形成源极/漏极结构，并在源极/漏极结构上形成金属层。 制造半导体结构的方法还包括使金属层的一部分与源极/漏极结构反应以在源极/漏极结构上形成金属层。 制造半导体结构的方法还包括通过蚀刻工艺去除金属层上的金属层的未反应部分。 此外，蚀刻工艺包括使用包括HF和碳酸丙烯酯的蚀刻剂，并且蚀刻剂中HF与碳酸亚丙酯的体积比在约1:10至约1：10000的范围内。

公开(公告)号：US11728169B2

公开(公告)日：2023-08-15

申请号：US17008016

申请日：2020-08-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki ,  Yasutoshi Okuno ,  Ta-Chun Ma

IPC分类号： H01L21/28 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311

CPC分类号： H01L21/28229 ,  H01L21/0206 ,  H01L21/31111 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02332

摘要： A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

公开(公告)号：US11101149B2

公开(公告)日：2021-08-24

申请号：US16933727

申请日：2020-07-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/3063 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  B82Y10/00 ,  C25F3/12 ,  H01L29/417 ,  C25F7/00 ,  H01L29/775 ,  H01L29/786 ,  H01L29/78 ,  C25D17/00 ,  H01L29/06 ,  H01L29/51

摘要： A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

公开(公告)号：US10468275B2

公开(公告)日：2019-11-05

申请号：US15717918

申请日：2017-09-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Andrew Joseph Kelly ,  Yusuke Oniki

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/3063 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  C25D17/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51

摘要： A method includes holding a semiconductor substrate by a substrate holder of an electrochemical apparatus. The electrochemical apparatus includes a reaction cell and a counter electrode, and the semiconductor substrate has an exposed surface containing germanium, silicon, silicon germanium or any of III-V elements. The exposed surface of the semiconductor substrate is immersed in an electrolyte bath in the reaction cell. A portion of the semiconductor substrate is removed by supplying a first current to the counter electrode and a second current to the semiconductor substrate. The second current has a negative bias. The negative bias is smaller than 0V and equal to or larger than minus 5V.