公开(公告)号：US07659162B2

公开(公告)日：2010-02-09

申请号：US12285531

申请日：2008-10-08

申请人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

发明人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

IPC分类号： H01L21/8242

CPC分类号： H01L45/12 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.

摘要翻译： 一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成 在顶部电极的上表面上和顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层 绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

公开(公告)号：US20060292795A1

公开(公告)日：2006-12-28

申请号：US11449848

申请日：2006-06-09

申请人： Sung-Un Kwon ,  Yong-Sun Ko ,  Jae-Seung Hwang

发明人： Sung-Un Kwon ,  Yong-Sun Ko ,  Jae-Seung Hwang

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/66825

摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.

摘要翻译： 在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。 在衬底中形成的沟槽被转换为沟槽结构。 在衬底上形成隧道氧化物层。 沟槽结构之间的空间填充有第一导电层。 去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。 在第一导电层图案和沟槽隔离结构上形成介电层。 在周边区域的基板上形成绝缘层。 在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。 分别在单元区域和外围区域中形成第一和第二栅极结构。

公开(公告)号：US07202163B2

公开(公告)日：2007-04-10

申请号：US10861863

申请日：2004-06-04

申请人： Sung-Un Kwon ,  Yong-Sun Ko

发明人： Sung-Un Kwon ,  Yong-Sun Ko

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76895

摘要： A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.

摘要翻译： 用于形成本发明的局部互连布线结构方法通过形成公共孔径来减小栅电极的局部互连层和有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径 半导体衬底的绝缘膜。 形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。 蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。 随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。 然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。 蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。 然后去除第二蚀刻掩模图案。 然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

公开(公告)号：US20090090899A1

公开(公告)日：2009-04-09

申请号：US12285531

申请日：2008-10-08

申请人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

发明人： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

IPC分类号： H01L45/00

CPC分类号： H01L45/12 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.

摘要翻译： 一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成 在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层 绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

公开(公告)号：US07498253B2

公开(公告)日：2009-03-03

申请号：US11679722

申请日：2007-02-27

申请人： Sung-Un Kwon ,  Yong-Sun Ko

发明人： Sung-Un Kwon ,  Yong-Sun Ko

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76895

摘要： A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.

摘要翻译： 用于形成其的局部互连配线结构方法通过形成公共孔径来减小栅电极的局部互连层与有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径 半导体衬底的绝缘膜。 形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。 蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。 随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。 然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。 蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。 然后去除第二蚀刻掩模图案。 然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

公开(公告)号：US07452773B2

公开(公告)日：2008-11-18

申请号：US11449848

申请日：2006-06-09

申请人： Sung-Un Kwon ,  Yong-Sun Ko ,  Jae-Seung Hwang

发明人： Sung-Un Kwon ,  Yong-Sun Ko ,  Jae-Seung Hwang

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/66825

摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.

摘要翻译： 在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。 在衬底中形成的沟槽被转换为沟槽结构。 在衬底上形成隧道氧化物层。 沟槽结构之间的空间填充有第一导电层。 去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。 在第一导电层图案和沟槽隔离结构上形成介电层。 在周边区域的基板上形成绝缘层。 在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。 分别在单元区域和外围区域中形成第一和第二栅极结构。

公开(公告)号：US08084801B2

公开(公告)日：2011-12-27

申请号：US12654255

申请日：2009-12-15

申请人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

发明人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/10888

摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

摘要翻译： 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。

公开(公告)号：US08053751B2

公开(公告)日：2011-11-08

申请号：US12591531

申请日：2009-11-23

申请人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

发明人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

IPC分类号： H01L21/4763

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

摘要翻译： 在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层 金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻 停止层与基底形成电连接。

公开(公告)号：US08048809B2

公开(公告)日：2011-11-01

申请号：US11898850

申请日：2007-09-17

申请人： Hyo-Jin Lee ,  Kyung-Hyun Kim ,  Yong-Sun Ko

发明人： Hyo-Jin Lee ,  Kyung-Hyun Kim ,  Yong-Sun Ko

IPC分类号： H01L21/302

CPC分类号： H01L21/7684 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/28123 ,  H01L21/3212

摘要： A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

摘要翻译： 浆料组合物包括约4.25至约18.5重量％的研磨剂，约80至约95重量％的去离子水和约0.05至约1.5重量％的添加剂。 浆料组合物还可以包括表面活性剂。 在使用浆料组合物的抛光方法中，可以快速抛光多晶硅层，并且可以抑制多晶硅层的凹陷和侵蚀。

公开(公告)号：US07781346B2

公开(公告)日：2010-08-24

申请号：US11455815

申请日：2006-06-20

申请人： Cheol-Woo Park ,  Byoung-Moon Yoon ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Kwang-Wook Lee

发明人： Cheol-Woo Park ,  Byoung-Moon Yoon ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Kwang-Wook Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/31111 ,  H01L21/0206 ,  H01L21/02068 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

摘要翻译： 可以通过使用含有蚀刻剂的湿法蚀刻工艺形成半导体结构。 半导体结构可以包括具有增加的或更高的纵横比的多个图案，并且可以彼此更靠近地布置。 可以在半导体结构上使用氟化氢气体进行干法处理。