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    Non-volatile memory devices having floating gates
    2.
    发明授权
    Non-volatile memory devices having floating gates 失效
    具有浮动门的非易失性存储器件

    公开(公告)号：US07592665B2

    公开(公告)日：2009-09-22

    申请号：US11594327

    申请日：2006-11-08

    申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

    NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE 审中-公开
    非易失性存储器件和用于制造器件的方法

    公开(公告)号：US20130181278A1

    公开(公告)日：2013-07-18

    申请号：US13608796

    申请日：2012-09-10

    申请人： Sung-Hun LEE ,  Sung-Hoi Hur ,  Jong-Ho Park

    发明人： Sung-Hun LEE ,  Sung-Hoi Hur ,  Jong-Ho Park

    IPC分类号： H01L29/792

    CPC分类号： H01L27/1157 ,  H01L21/764 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

    摘要： Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps.

    摘要翻译： 提供了一种非易失性存储器件，其包括：衬底，其包括在第一方向上延伸的多个有源区和设置在有源区之间的多个元件隔离沟槽;多个隧道绝缘层图案和多个存储层图案 顺序地设置在基板上，多个阻挡绝缘层和多个栅电极，其设置在存储层图案上并沿垂直于第一方向的第二方向延伸，并且第一绝缘层包括设置在第一方向上的有源区之间的气隙 元件隔离沟槽并沿第一方向延伸，其中有源区包括与第一有源区相邻的第一有源区和第二有源区，其中第一气隙的宽度不同于第二气隙的宽度。

    Non-volatile memory devices having floating gates and related methods of forming the same
    4.
    发明申请
    Non-volatile memory devices having floating gates and related methods of forming the same 失效
    具有浮动栅极的非易失性存储器件及其相关方法

    公开(公告)号：US20070108498A1

    公开(公告)日：2007-05-17

    申请号：US11594327

    申请日：2006-11-08

    申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

    Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same
    5.
    发明授权
    Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same 有权
    半导体存储器件包括在隔离栅侧壁上的双重间隔物，包括该隔离栅的电子器件

    公开(公告)号：US07671400B2

    公开(公告)日：2010-03-02

    申请号：US12133587

    申请日：2008-06-05

    申请人： Joon-Sung Lim ,  Jong-Ho Park ,  Hyun-Chul Back ,  Sung-Hun Lee

    发明人： Joon-Sung Lim ,  Jong-Ho Park ,  Hyun-Chul Back ,  Sung-Hun Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.

    摘要翻译： 半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。 浮动门设置在活动区域​​上。 控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。 控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。 第一间隔件设置在相邻浮动门的侧壁上。 每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。 第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。 还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

    FEMTO ACCESS POINT AND METHOD FOR AUTOMATICALLY SETTING AREA CODE
    8.
    发明申请
    FEMTO ACCESS POINT AND METHOD FOR AUTOMATICALLY SETTING AREA CODE 审中-公开
    FEMTO接入点和自动设置区域代码的方法

    公开(公告)号：US20120088496A1

    公开(公告)日：2012-04-12

    申请号：US13266384

    申请日：2010-04-21

    申请人： Ki-Ho Lee ,  Hee-Jun Lee ,  Joong-Wan Park ,  Jong-Ho Park

    发明人： Ki-Ho Lee ,  Hee-Jun Lee ,  Joong-Wan Park ,  Jong-Ho Park

    IPC分类号： H04W4/00

    CPC分类号： H04W24/02 ,  H04W8/26 ,  H04W28/06 ,  H04W48/16 ,  H04W84/045

    摘要： Provided is a method for automatically setting an area code by a femto access point (AP) located in a coverage area of a macro cell. The method includes receiving a broadcast signal of the macro cell, extracting an area code of the macro cell from the received broadcast signal, and setting the extracted area code as an area code of the femto cell. The femto AP sets the same area code as that of the macro cell as its area code and transmits the area code of the femto AP to the mobile station, thereby preventing the mobile station from repeating the location registration and enabling the mobile station to receive the same paging message from the femto AP and the macro cell.

    摘要翻译： 提供了一种通过位于宏小区的覆盖区域中的毫微微接入点（AP）自动设置区域码的方法。 该方法包括接收宏小区的广播信号，从接收到的广播信号中提取宏小区的区域码，并将所提取的区域码设置为毫微微小区的区域码。 毫微微AP设置与宏小区相同的区域码作为其区号，并将毫微微AP的区域码发送到移动台，从而防止移动台重复位置登记，并使移动台能够接收 来自毫微微AP和宏小区的相同寻呼消息。

    Video signal processing device and method of processing gradation
    10.
    发明申请
    Video signal processing device and method of processing gradation 失效
    视频信号处理装置及其处理方法

    公开(公告)号：US20090167957A1

    公开(公告)日：2009-07-02

    申请号：US12318407

    申请日：2008-12-29

    申请人： Mi-Young Joo ,  Jong-Ho Park

    发明人： Mi-Young Joo ,  Jong-Ho Park

    IPC分类号： H04N5/57

    CPC分类号： G06T5/008 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/20012 ,  G09G3/2059 ,  G09G5/00 ,  G09G2320/0626 ,  G09G2320/0646 ,  G09G2320/066 ,  G09G2320/106 ,  G09G2330/021 ,  G09G2340/16 ,  G09G2360/16

    摘要： Disclosed is a video signal processing device and a method of processing gradation capable of improving the contrast ratio and the user satisfaction of a plasma display device. The video signal processing device includes a position detecting unit for detecting positions of pixels to be displayed in a frame, a sub region detecting unit for detecting a central region including a reference point formed of at least one pixel in the frame and sub regions surrounding the central region, and a compensating unit for differently compensating brightness of pixels positioned in the sub regions and brightness of pixels positioned in the central unit.

    摘要翻译： 公开了一种视频信号处理装置和处理能够提高等离子体显示装置的对比度和用户满意度的等级的方法。 视频信号处理装置包括：位置检测单元，用于检测要在帧中显示的像素的位置;子区域检测单元，用于检测包括由帧中的至少一个像素形成的参考点的中心区域; 中央区域和用于不同地补偿位于子区域中的像素的亮度和位于中央单元中的像素的亮度的补偿单元。