公开(公告)号：US09484354B2

公开(公告)日：2016-11-01

申请号：US14637538

申请日：2015-03-04

申请人： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

发明人： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/04

CPC分类号： H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045

摘要： A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

摘要翻译： 存储器件包括在衬底的第一区域上的存储器单元。 有源区域位于与衬底的第一区域相邻的第二区域中，并且有源区域的延伸方向与衬底的<110>方向成锐角。 用作外围电路的晶体管位于衬底的第二区域上。 在存储器件中，由于晶体缺陷或衬底的位错导致的缺陷或故障可能降低。

公开(公告)号：US06908819B2

公开(公告)日：2005-06-21

申请号：US10360881

申请日：2003-02-07

申请人： Hee-Jueng Lee ,  Myung-Ho Ko

发明人： Hee-Jueng Lee ,  Myung-Ho Ko

IPC分类号： H01L21/762 ,  H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/11253 ,  H01L21/76213 ,  H01L27/112

摘要： According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the semiconductor substrate. Next, the mask pattern is removed to expose the first gate insulating pattern and a second gate insulating layer is formed on the entire surface thereof. The mask pattern is preferably formed of an anti-reflecting pattern and a photoresist pattern that are sequentially stacked. The anti-reflecting pattern is preferably formed of a material layer without etching selectivity with respect to the photoresist pattern. For this, the anti-reflecting pattern is preferably formed of organic materials including hydrocarbonic compounds. In addition, removing a mask pattern is performed with an etch recipe having an etch selectivity with respect to the first gate insulating pattern.

摘要翻译： 根据本发明的实施例，第一栅极绝缘图案和掩模图案依次层叠在半导体衬底上。 随后在半导体衬底中形成杂质区。 接下来，去除掩模图案以暴露第一栅极绝缘图案，并且在其整个表面上形成第二栅极绝缘层。 掩模图案优选由依次层叠的抗反射图案和光致抗蚀剂图案形成。 防反射图案优选由相对于光致抗蚀剂图案而没有蚀刻选择性的材料层形成。 为此，抗反射图案优选由包括烃化合物的有机材料形成。 此外，使用具有相对于第一栅绝缘图案的蚀刻选择性的蚀刻配方来执行去除掩模图案。

公开(公告)号：US07608500B2

公开(公告)日：2009-10-27

申请号：US11671994

申请日：2007-02-06

申请人： Byung-Kwan You ,  Jun-Eui Song ,  Gyeong-Hee Kim ,  Hee-Jueng Lee

发明人： Byung-Kwan You ,  Jun-Eui Song ,  Gyeong-Hee Kim ,  Hee-Jueng Lee

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823462 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546

摘要： Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

摘要翻译： 提供一种形成半导体器件的方法。 在具有单元区域和低电压区域的基板上形成隧道绝缘层。 第一和第二电荷存储栅极图案（例如，浮栅图案）分别形成在电池和低电压区域的隧道绝缘层上。 依次在基板上形成阻挡绝缘层和控制栅极导电层。 除去低电压区域的控制栅极导电层，阻挡绝缘层，第二浮栅图案和隧道绝缘层，露出低电压区域的基板。 低压栅极绝缘层形成在暴露的基板上。 在低压栅极绝缘层上形成低压栅极导电图案。

公开(公告)号：US06716704B2

公开(公告)日：2004-04-06

申请号：US10085369

申请日：2002-02-28

申请人： Hee-Jueng Lee ,  Ki-Chang Yoon

发明人： Hee-Jueng Lee ,  Ki-Chang Yoon

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/28273 ,  H01L29/66825

摘要： A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

摘要翻译： 通过在集成电路基板上的绝缘层上形成包括侧壁的第一导电层图案来制造ROM器件。 使用第一导电层图案作为注入掩模将离子注入集成电路基板。 集成电路基板的至少一部分以及侧壁的至少一部分被热氧化，以在集成电路基板的至少一部分和侧壁上形成热氧化物层，并形成掩埋掺杂层 来自热氧化物层下方的注入离子。 然后在热氧化物层的至少一部分上和第一导电层图案的至少一部分上形成第二导电层图案。