公开(公告)号：US20100171148A1

公开(公告)日：2010-07-08

申请号：US12725792

申请日：2010-03-17

Applicant: Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

Inventor： Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

IPC: H01L27/06

CPC classification number: H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N− well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N− well, a P+ diffusion region in contact with the N− well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

Abstract translation: 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电极的连通结构和形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区和N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US20100161304A1

公开(公告)日：2010-06-24

申请号：US12494031

申请日：2009-06-29

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045

Abstract: A method for designing a semiconductor device circuit comprising a electrostatic discharge (ESD) protection circuit can include device simulations using at least one, for example two or more ESD models, and designing device features such that they are resilient to damage from the two or more ESD testing models.

Abstract translation: 一种用于设计包括静电放电（ESD）保护电路的半导体器件电路的方法可以包括使用至少一个，例如两个或更多个ESD模型的设备模拟，以及设计器件特征，使得它们具有弹性以抵抗来自两个或更多个 ESD测试模型。

公开(公告)号：US20100321842A1

公开(公告)日：2010-12-23

申请号：US12489774

申请日：2009-06-23

Applicant: Ephrem G. GEBRESELASIE ,  Steven H. VOLDMAN

Inventor： Ephrem G. GEBRESELASIE ,  Steven H. VOLDMAN

IPC: H02H9/00 ,  H01L21/3205

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

Abstract translation: 提供了具有与通过晶片通孔结构和制造方法的连接的静电放电（ESD）结构。 该结构包括与通过晶片通孔串联电连接的静电放电（ESD）网络。 更具体地，ESD电路包括位于接合焊盘下方的接合焊盘和ESD网络。 ESD电路还包括直接与ESD网络串联电连接并且还电连接到VSS的直通晶片通孔结构。

公开(公告)号：US20080254609A1

公开(公告)日：2008-10-16

申请号：US11871713

申请日：2007-10-12

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: H01L21/44

CPC classification number: H01L23/5256 ,  H01L27/0248 ,  H01L2924/0002 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Method of making an electronic fuse blow resistor structure. In one embodiment, the method includes forming an insulator film, depositing a conductor on the insulator film, and after the depositing, etching the conductor to form a plurality of spaced apart non-conductive regions and a plurality of spaced-apart conductive regions. In another embodiment, the method includes forming the insulator film, forming a conductive sheet, and sub-dividing the conductive sheet into the plurality of conductive regions.

Abstract translation: 制造电子熔断器电阻器结构的方法。 在一个实施例中，该方法包括形成绝缘体膜，在绝缘膜上沉积导体，以及在沉积之后蚀刻导体以形成多个间隔开的非导电区域和多个间隔开的导电区域。 在另一个实施例中，该方法包括形成绝缘膜，形成导电片，并将导电片分割成多个导电区域。

公开(公告)号：US20120124533A1

公开(公告)日：2012-05-17

申请号：US13358105

申请日：2012-01-25

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.

Abstract translation: 公开了一种避免闩锁的方法和半导体结构。 该方法包括识别半导体芯片上的至少一个高电压器件，识别半导体芯片上的由保护环与所识别的至少一个高电压器件分离的电路，评估该电路的闩锁状态，以及当 发生闩锁状态，调整电路中的接触电路间距。

公开(公告)号：US20110227166A1

公开(公告)日：2011-09-22

申请号：US13150437

申请日：2011-06-01

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: H01L27/092 ,  G06F17/50

CPC classification number: H01L27/0921

Abstract: A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

Abstract translation: 用于防止闩锁的结构。 该结构包括闭锁敏感结构和限制闩锁敏感结构的穿透晶片通孔结构，以防止寄生载流子注入到闩锁敏感结构中。

公开(公告)号：US20110227130A1

公开(公告)日：2011-09-22

申请号：US13150440

申请日：2011-06-01

Applicant: Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

Inventor： Xuefeng LIU ,  Robert M. RASSEL ,  Steven H. VOLDMAN

IPC: H01L29/12 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

Abstract translation: 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US20110198703A1

公开(公告)日：2011-08-18

申请号：US13095158

申请日：2011-04-27

Applicant: Phillip F. CHAPMAN ,  David S. COLLINS ,  Steven H. VOLDMAN

Inventor： Phillip F. CHAPMAN ,  David S. COLLINS ,  Steven H. VOLDMAN

IPC: H01L27/092 ,  H01L21/02

CPC classification number: H01L27/0921 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract translation: 一种制造半导体结构的方法包括：在衬底的背面形成沟槽; 在沟槽的表面上沉积掺杂剂; 在与沟槽相对的衬底的顶侧中形成浅沟槽隔离（STI）结构; 在基材中形成深井; 将掺杂剂扩散到深阱和衬底中; 在衬底中形成N阱和P阱; 并用导电材料填充沟槽。

公开(公告)号：US20100244187A1

公开(公告)日：2010-09-30

申请号：US12411612

申请日：2009-03-26

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: H01L29/861 ,  H01L21/02

CPC classification number: H01L27/0248 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/60 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The present invention generally relates to a circuit structure and a method of manufacturing a circuit, and more specifically to an electrostatic discharge (ESD) circuit with a through wafer via structure and a method of manufacture. An ESD structure includes an ESD active device and at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate. An apparatus includes an input, at least one power rail and an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate. A method, includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

Abstract translation: 本发明一般涉及一种电路结构及其制造方法，更具体地说涉及一种具有贯通晶片通孔结构和制造方法的静电放电（ESD）电路。 ESD结构包括ESD有源器件和至少一个贯穿晶片通孔结构，其提供用于ESD有源器件到衬底的低串联电阻通路。 一种装置包括输入，至少一个电源轨和ESD电路，电连接在输入和至少一个电源轨之间，其中ESD电路包括提供到衬底的低串联电阻路径的至少一个贯通晶片通孔结构。 一种方法，包括在衬底上形成ESD有源器件，在衬底的背面形成接地平面，并通过电连接到ESD有源器件和接地平面的负电源，形成至少一个通过晶片，从而提供 低的串联电阻路径到基板。

公开(公告)号：US20090070718A1

公开(公告)日：2009-03-12

申请号：US12124551

申请日：2008-05-21

Applicant: Steven H. VOLDMAN

Inventor： Steven H. VOLDMAN

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes is formed. The placement of the at least one functional circuit block is modified relative to other functional circuit blocks based on the element density function to substantially eliminate latching effects in a circuit.

Abstract translation: 一种用于最小化对锁存器的灵敏度的电路的结构，装置和方法。 该方法包括例如识别至少一个功能电路块的元件密度和与至少一个功能电路块相关联的元件的元件属性。 形成从元素属性参数化的元素密度函数。 基于元件密度函数，至少一个功能电路块的布置相对于其他功能电路块进行修改，以基本上消除电路中的锁存效应。