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    Reducing false positives in configuration error detection for programmable devices
    1.
    发明授权
    Reducing false positives in configuration error detection for programmable devices 有权
    减少可编程器件配置错误检测中的误报

    公开(公告)号：US07620876B2

    公开(公告)日：2009-11-17

    申请号：US11407519

    申请日：2006-04-19

    Applicant: David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    Inventor： David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    IPC: G11C29/00

    CPC classification number: G11C29/42 ,  G06F11/1008 ,  G11C29/52

    Abstract: A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.

    Abstract translation: 设备通过使用掩蔽单元和灵敏度掩码数据来减少假阳性存储器错误检测，以从错误检测计算中排除存储器的未使用部分。 一种设备包括一个错误检测单元，用于从存储器读取数据并验证数据完整性。 灵敏度掩码数据指示存储器的未使用部分。 存储器的未使用部分可以对应于可编程设备的未使用部分的配置数据。 灵敏度掩码数据的每一位可以指示来自存储器的数据的一位或多位的使用。 响应于掩模数据，掩蔽单元将来自存储器的未使用部分的数据设置为不改变错误检测计算结果的值。 这防止来自存储器的未使用部分的数据中的任何错误引起错误信号。

    Programmable logic device with hierarchical interconnection resources
    2.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06417694B1

    公开(公告)日：2002-07-09

    申请号：US09956748

    申请日：2001-09-19

    Applicant: Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    Inventor： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC: H03K19177

    CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    Abstract translation: 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Programmable logic device with redundant circuitry
    5.
    发明授权
    Programmable logic device with redundant circuitry 有权
    具有冗余电路的可编程逻辑器件

    公开(公告)号：US06201404B1

    公开(公告)日：2001-03-13

    申请号：US09295672

    申请日：1999-04-20

    Applicant: Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    Inventor： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    IPC: H03K19003

    CPC classification number: H03K19/17764 ,  H03K19/17736

    Abstract: A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

    Abstract translation: 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

    Programmable logic device with low power voltage level translator
    8.
    发明授权
    Programmable logic device with low power voltage level translator 失效
    具有低功率电压电平转换器的可编程逻辑器件

    公开(公告)号：US5432467A

    公开(公告)日：1995-07-11

    申请号：US324312

    申请日：1994-10-17

    Applicant: Srinivas T. Reddy

    Inventor： Srinivas T. Reddy

    IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0948

    CPC classification number: H03K19/0013 ,  H03K19/018521

    Abstract: A voltage translation circuit 6 and method of operating a circuit to provide voltage level translation, particularly for use in association with a programmable logic device 2. An input signal, is provided to an NMOS transistor N2 and a CMOS inverter 12. The inverter 12 drives an NMOS pulldown transistor N4. The drain of N2 is coupled to the input of an inverter 14, the output of which is also coupled to the translation circuit output. A source of PMOS pullup transistor P1 drives the input of inverter 14 to pullup the output to a high level.

    Abstract translation: 电压转换电路6和操作电路以提供电压电平转换的方法，特别是与可编程逻辑器件2相关联地使用。输入信号提供给NMOS晶体管N2和CMOS反相器12.反相器12驱动 一个NMOS下拉晶体管N4。 N2的漏极耦合到反相器14的输入，反相器14的输出也耦合到平移电路输出。 PMOS上拉晶体管P1的源极驱动反相器14的输入以将输出上拉至高电平。

    Reduced noise output buffer
    9.
    发明授权
    Reduced noise output buffer 失效
    降噪输出缓冲器

    公开(公告)号：US5315172A

    公开(公告)日：1994-05-24

    申请号：US868399

    申请日：1992-04-14

    Applicant: Srinivas T. Reddy

    Inventor： Srinivas T. Reddy

    IPC: H03K17/16

    CPC classification number: H03K17/164

    Abstract: The output buffer includes first and second N channel FETs serially connected between a ground terminal and a voltage supply terminal and having a common terminal connected to an output terminal. Third and fourth N channel FETs are serially connected between the ground terminal and the voltage supply terminal and have a common terminal connected to the output terminal. A first logic circuit responds to data input (DIN) signals and an operation enable bar (OEB) signal for applying a conductive bias voltage to the third N channel FET, and a second logic circuit responds to the DIN signals and the OEB signal for applying a conductive bias voltage to the fourth N channel FET. A first P channel FET couples the conductive bias voltage on the third N channel FET to the first N channel FET, and a second P channel FET couples the conductive bias on the fourth N channel FET to the second N channel FET. The P channel transistors are mask programmable weak conductors thus limiting the rate of conductive bias applied to the first N channel FET and to the second N channel FET. Fifth and sixth N channel FETs are connected between the gate terminals of the first and second FETs and circuit ground for preventing conduction of the first and second FETs when the fifth and sixth FETs are conductive.

    Abstract translation: 输出缓冲器包括串联连接在接地端子和电压源端子之间并具有连接到输出端子的公共端子的第一和第二N沟道FET。 第三和第四N沟道FET串联连接在接地端子和电源端子之间，并具有连接到输出端子的公共端子。 第一逻辑电路响应于数据输入（DIN）信号和用于向第三N沟道FET施加导电偏置电压的操作使能条（OEB）信号，第二逻辑电路响应DIN信号和OEB信号以施加 到第四N沟道FET的导电偏置电压。 第一P沟道FET将第三N沟道FET上的导电偏置电压耦合到第一N沟道FET，而第二P沟道FET将第四N沟道FET上的导电偏压耦合到第二N沟道FET。 P沟道晶体管是掩模可编程弱导体，从而限制施加到第一N沟道FET和第二N沟道FET的导电偏压的速率。 第五和第六N沟道FET连接在第一和第二FET的栅极端子和电路接地之间，以防止当第五和第六FET导通时第一和第二FET导通。

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