Invention Grant
US06879183B2 Programmable logic device architectures with super-regions having logic regions and a memory region
有权
具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
- Patent Title: Programmable logic device architectures with super-regions having logic regions and a memory region
- Patent Title (中): 具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
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Application No.: US10260712Application Date: 2002-09-27
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Publication No.: US06879183B2Publication Date: 2005-04-12
- Inventor: David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
- Applicant: David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Fish and Neave
- Agent Robert R. Jackson; Jeffrey C. Aldridge
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H03K19/173 ; H03K19/177
Abstract:
A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
Public/Granted literature
- US20030080778A1 Programmable logic device architectures with super-regions having logic regions and a memory region Public/Granted day:2003-05-01
Information query
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