METHOD FOR FORMING A HIGH QUALITY INSULATION LAYER ON A SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD FOR FORMING A HIGH QUALITY INSULATION LAYER ON A SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件上形成高质量绝缘层的方法

    公开(公告)号:US20100261355A1

    公开(公告)日:2010-10-14

    申请号:US12493279

    申请日:2009-06-29

    CPC classification number: H01L21/31608 H01L21/02164 H01L21/02271

    Abstract: A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step.

    Abstract translation: 提出了一种在半导体器件上形成高品质绝缘层的方法。 该方法包括将硅源气体和氧源气体中的任一种供给到其中放置半导体衬底的处理室中的第一步骤; 将硅源气体和氧源气体同时供给到已经经历了第一步骤的处理室中并在半导体衬底上沉积氧化硅层的第二步骤; 以及将硅源气体和氧源气体中的任一种供给到经过第二工序的处理室的第三工序。

    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING THE DECREASE OF THE WIDTH OF AN ACTIVE REGION
    5.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING THE DECREASE OF THE WIDTH OF AN ACTIVE REGION 有权
    制造能够防止活跃区域宽度减小的半导体器件的方法

    公开(公告)号:US20090162990A1

    公开(公告)日:2009-06-25

    申请号:US12100455

    申请日:2008-04-10

    CPC classification number: H01L21/823481 H01L21/76224

    Abstract: A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.

    Abstract translation: 描述了可以防止隔离结构的损失并且还可以稳定地形成外延硅层的半导体器件的制造方法。 半导体器件的制造方法包括在具有有源区和隔离区的半导体衬底中限定沟槽。 沟槽部分地填充有第一绝缘层。 在填充有第一绝缘层的沟槽的表面上形成蚀刻保护层。 在由蚀刻保护层形成的沟槽中填充第二绝缘层,以在半导体衬底的隔离区域中形成隔离结构。 最后,半导体衬底的有源区的部分被凹入,使得隔离结构的高度高于半导体衬底的有源区。

    METHOD FOR FORMING DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE USING ANNEALING STEPS TO ANNEAL FLOWABLE INSULATION LAYER
    6.
    发明申请
    METHOD FOR FORMING DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE USING ANNEALING STEPS TO ANNEAL FLOWABLE INSULATION LAYER 失效
    使用退火步骤形成半导体器件的器件隔离结构的方法可用于可流动的绝缘层

    公开(公告)号:US20090035917A1

    公开(公告)日:2009-02-05

    申请号:US12045073

    申请日:2008-03-10

    Abstract: A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.

    Abstract translation: 提出了使用至少三个退火步骤形成半导体器件的器件隔离结构以退火可流动绝缘层的方法。 该方法包括以下步骤:在具有暴露半导体衬底的器件隔离区域的有源区的半导体衬底上形成硬掩模图案; 蚀刻通过硬掩模图案曝光的半导体衬底的器件隔离区,并且其中形成沟槽; 形成可流动的绝缘层以填充沟槽; 首先将可流动绝缘层退火至少三次; 对所述第一退火可流动绝缘层进行第二退火; 去除所述第二退火的可流动绝缘层,直到所述硬掩模图案被暴露; 并去除暴露的硬掩模图案。

    METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE
    8.
    发明申请
    METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE 有权
    使用交叉图形技术制造相位变化记忆装置的方法

    公开(公告)号:US20110143477A1

    公开(公告)日:2011-06-16

    申请号:US12834141

    申请日:2010-07-12

    Abstract: A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.

    Abstract translation: 提供一种制造相变存储器件的方法。 在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。 形成具有阻挡金属层,多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。 在线路结构之间形成第二绝缘层。 通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。 第三绝缘层埋在交叉图案之间的空间内。 形成自对准的相变接触孔,同时,通过选择性地去除构成交叉图案的硬掩模层,形成由剩余多晶硅层形成的二极管图案。

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