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    Method of manufacturing semiconductor device for formation of pin transistor
    3.
    发明授权
    Method of manufacturing semiconductor device for formation of pin transistor 有权
    用于形成pin晶体管的半导体器件的制造方法

    公开(公告)号：US07563654B2

    公开(公告)日：2009-07-21

    申请号：US11647759

    申请日：2006-12-29

    Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

    Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An ,  Hyun Chul Sohn

    IPC: H01L21/335

    CPC classification number: H01L27/0886 ,  H01L27/1214

    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

    Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A SPACER AS AN ETCH MASK FOR FORMING A FINE PATTERN
    5.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A SPACER AS AN ETCH MASK FOR FORMING A FINE PATTERN 有权
    使用间隔器作为形成微细图案的蚀刻掩模制造半导体器件的方法

    公开(公告)号：US20090001044A1

    公开(公告)日：2009-01-01

    申请号：US11939215

    申请日：2007-11-13

    Applicant: Chai O. CHUNG ,  Jong Min LEE ,  Chan Bae KIM ,  Hyeon Ju AN ,  Hyo Seok LEE ,  Sung Kyu MIN

    Inventor： Chai O. CHUNG ,  Jong Min LEE ,  Chan Bae KIM ,  Hyeon Ju AN ,  Hyo Seok LEE ,  Sung Kyu MIN

    IPC: C23F1/00

    CPC classification number: H01L21/0337 ,  H01L21/0338

    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.

    Abstract translation: 描述了使用间隔物作为用于形成精细图案的蚀刻掩模的半导体器件的制造方法。 该方法包括在期望蚀刻的目标层上形成硬掩模层。 随后在硬掩模层上形成牺牲层图案。 隔板形成在牺牲层图案的侧壁上。 在由间隔物形成的牺牲图案之间的硬掩模层部分上形成保护层。 然后分别去除牺牲层图案和保护层。 使用间隔物作为蚀刻掩模蚀刻硬掩模层。 蚀刻后，移除间隔物。 最后，使用蚀刻的硬掩模作为蚀刻掩模蚀刻目标层。

    SEMICONDUCTOR DEVICE HAVING REDUCED STANDBY LEAKAGE CURRENT AND INCREASED DRIVING CURRENT AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING REDUCED STANDBY LEAKAGE CURRENT AND INCREASED DRIVING CURRENT AND METHOD FOR MANUFACTURING THE SAME 失效
    具有降低的待机泄漏电流和增加的驱动电流的半导体器件及其制造方法

    公开(公告)号：US20080079076A1

    公开(公告)日：2008-04-03

    申请号：US11776885

    申请日：2007-07-12

    Applicant: Dong Sun SHEEN ,  Sang Tae AHN ,  Seok Pyo SONG ,  Hyeon Ju AN

    Inventor： Dong Sun SHEEN ,  Sang Tae AHN ,  Seok Pyo SONG ,  Hyeon Ju AN

    IPC: H01L27/12 ,  H01L21/336

    CPC classification number: H01L29/78609 ,  H01L29/66795 ,  H01L29/7851

    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

    Abstract translation: 半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

    Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation
    8.
    发明授权
    Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation 失效
    形成半导体器件的隔离结构的方法，用于防止在凹陷栅极形成期间的过度损耗

    公开(公告)号：US07687371B2

    公开(公告)日：2010-03-30

    申请号：US12243133

    申请日：2008-10-01

    Applicant: Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

    Inventor： Dong Sun Sheen ,  Seok Pyo Song ,  Sang Tae Ahn ,  Hyeon Ju An

    IPC: H01L21/76

    CPC classification number: H01L21/76224

    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

    Abstract translation: 半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。 通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。 在包含SOG层的所得基板上形成无定形氧化铝层。 在无定形氧化铝层上形成HDP层以完全填充沟槽。 对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。 去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。 无定形氧化铝层结晶。

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