FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF

    公开(公告)号:US20230084175A1

    公开(公告)日:2023-03-16

    申请号:US17983929

    申请日:2022-11-09

    Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

    FLIP FLOP INCLUDING SERIAL STACK STRUCTURE TRANSISTORS

    公开(公告)号:US20220337231A1

    公开(公告)日:2022-10-20

    申请号:US17712465

    申请日:2022-04-04

    Abstract: A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

    WASHING MACHINE AND METHOD FOR CONTROLLING SAME

    公开(公告)号:US20200308749A1

    公开(公告)日:2020-10-01

    申请号:US16303129

    申请日:2016-12-21

    Abstract: According to the present invention, it is appropriately determined whether there is a portent of abnormal vibration or not, and an appropriate control is conducted such that no abnormal vibration occurs during a dewatering stroke. A control unit comprises a calculation unit, a determination unit, and a motor rotation control unit. The calculation unit calculates the rate of change in water level, which indicates the amount of change in water level per a predetermined period of time, on the basis of the result of sensing by a water level sensor in connection with a water supply stroke. The determination unit determines whether laundry having a waterproof property is contained in a drum or not on the basis of the rate of change in water level during the water supply stroke calculated by the calculation unit. When it is determined that laundry having a waterproof property is contained in the drum, the motor rotation control unit controls the operation of a driving motor such that the drum is rotated at a predetermined number of rotations or less during the dewatering stroke.

    FLIP-FLOP CIRCUIT
    8.
    发明申请
    FLIP-FLOP CIRCUIT 审中-公开
    FLIP-FLOP电路

    公开(公告)号:US20150303901A1

    公开(公告)日:2015-10-22

    申请号:US14754926

    申请日:2015-06-30

    Inventor: Minsu KIM

    CPC classification number: H03K3/356 H03K3/356173

    Abstract: A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node, and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged.

    Abstract translation: 触发器电路包括连接到第一节点的评估部分和第二节点,以根据第一节点的电压电平来放电第二节点;条件延迟部分,连接到第二节点,以将第三节点放电以具有 电压电平不同于第二节点的电压电平,以及连接到第二节点和第三节点的保持器逻辑部分,以维持第二和第三节点之一的电压电平不被放电。

    DATA DISPLAY APPARATUS AND METHOD FOR MOBILE TERMINAL
    9.
    发明申请
    DATA DISPLAY APPARATUS AND METHOD FOR MOBILE TERMINAL 审中-公开
    数据显示装置和移动终端的方法

    公开(公告)号:US20130106810A1

    公开(公告)日:2013-05-02

    申请号:US13655794

    申请日:2012-10-19

    Abstract: An apparatus and a method for a mobile terminal are provided. The data display apparatus includes a control unit, having a frame buffer, for identifying a frame rate of an application to be executed, for notifying, when the application is executable in a limited operation mode using a frame rate lower than a default frame rate set for a normal operation mode, the frame rate lower than the default frame rate and a clock frequency corresponding to the lower frame rate, and for storing, during execution of the application, display data of the application in the frame buffer at the lower frame rate, and a display unit, having a display controller, for accessing, when a frame rate and clock frequency is notified by the control unit, the frame buffer at the notified clock frequency, and for displaying screen data stored in the frame buffer at the notified frame rate.

    Abstract translation: 提供了一种用于移动终端的装置和方法。 数据显示装置包括具有帧缓冲器的控制单元,用于识别要执行的应用程序的帧速率,以便当使用低于默认帧速率集合的帧速率在有限操作模式下执行应用时通知 对于正常操作模式,帧速率低于默认帧速率和对应于较低帧速率的时钟频率,并且用于在执行应用期间以较低帧速率在帧缓冲器中显示应用的数据 以及具有显示控制器的显示单元,用于当通过控制单元通知帧速率和时钟频率时,以通知的时钟频率访问帧缓冲器,并且用于在所通知的时间显示存储在帧缓冲器中的屏幕数据 帧速率。

    DC-DC CONVERTER AND POWER DEVICE INCLUDING THE SAME

    公开(公告)号:US20230170795A1

    公开(公告)日:2023-06-01

    申请号:US17993603

    申请日:2022-11-23

    CPC classification number: H02M3/07 H02M1/0012 H02M1/08 H02M1/0054

    Abstract: The present disclosure refers to direct current-to-direct current (DC-DC) converters and power supplies including the same. In an embodiment, a DC-DC converter includes a first switching circuit, a second switching circuit, a fourth capacitor coupled to a second node, and an inductor-capacitor (LC) filter coupled to a third node. The first switching circuit includes a first transistor coupled between a first capacitor and an input node, a second transistor coupled between the first capacitor and a second capacitor, a third transistor coupled between a first node and a third capacitor, and a fourth transistor coupled between the third capacitor and a ground node. The second switching circuit includes a fifth transistor coupled between the second capacitor and the third capacitor, a sixth transistor and a seventh transistor coupled between the first capacitor and the third capacitor, and an eighth transistor coupled between the first capacitor and the ground node.

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