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    LOW POWER CLOCK GATING CELL AND AN INTEGRATED CIRCUIT INCLUDING THE SAME
    1.
    发明申请
    LOW POWER CLOCK GATING CELL AND AN INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20220166427A1

    公开(公告)日：2022-05-26

    申请号：US17515607

    申请日：2021-11-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunchul HWANG ,  Youngo LEE

    IPC: H03K17/687 ,  H03K3/356

    Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF
    2.
    发明申请
    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210152161A1

    公开(公告)日：2021-05-20

    申请号：US16930658

    申请日：2020-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongwoo KIM ,  Minsu KIM ,  Yonggeol KIM ,  Hyun LEE ,  Hyunchul HWANG

    IPC: H03K3/037 ,  H03K19/00

    Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

    SEQUENTIAL CIRCUIT AND OPERATING METHOD THEREOF
    4.
    发明申请
    SEQUENTIAL CIRCUIT AND OPERATING METHOD THEREOF 审中-公开
    其顺序电路及其操作方法

    公开(公告)号：US20170070215A1

    公开(公告)日：2017-03-09

    申请号：US15254272

    申请日：2016-09-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunchul HWANG ,  Minsu KIM

    IPC: H03K3/356 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20 ,  G11C11/4074

    CPC classification number: H03K3/356121 ,  G11C7/1006 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20

    Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

    Abstract translation: 在顺序电路中，第一级被配置为响应于时钟对第一节点的电压进行充电，并且响应于时钟，第二节点的电压和数据来放电第一节点的电压; 第二级被配置为响应于时钟对第二节点的电压进行充电，并且响应于时钟和逻辑信号来放电第二节点的电压; 组合逻辑被配置为基于第一节点的电压，第二节点的电压和数据来生成逻辑信号; 并且锁存电路被配置为响应于时钟来锁存第二节点的电压。

    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF
    5.
    发明申请
    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230084175A1

    公开(公告)日：2023-03-16

    申请号：US17983929

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongwoo KIM ,  Minsu KIM ,  Yonggeol KIM ,  Hyun LEE ,  Hyunchul HWANG

    IPC: H03K3/037 ,  H03K19/00 ,  H03K3/3562

    Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

    FLIP FLOP INCLUDING SERIAL STACK STRUCTURE TRANSISTORS
    6.
    发明申请
    FLIP FLOP INCLUDING SERIAL STACK STRUCTURE TRANSISTORS 有权

    公开(公告)号：US20220337231A1

    公开(公告)日：2022-10-20

    申请号：US17712465

    申请日：2022-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunchul HWANG ,  Minsu KIM

    IPC: H03K3/356 ,  H03K3/013 ,  H03K3/012

    Abstract: A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

    CIRCUIT PERFORMING LOGICAL OPERATION AND FLIP-FLOP INCLUDING THE CIRCUIT
    7.
    发明申请
    CIRCUIT PERFORMING LOGICAL OPERATION AND FLIP-FLOP INCLUDING THE CIRCUIT 有权

    公开(公告)号：US20220158640A1

    公开(公告)日：2022-05-19

    申请号：US17503791

    申请日：2021-10-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunchul HWANG ,  Minsu KIM ,  Janghwan YOON

    IPC: H03K19/096 ,  H03K19/20

    Abstract: An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.

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