公开(公告)号：US10153292B2

公开(公告)日：2018-12-11

申请号：US15907667

申请日：2018-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L49/02

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US10553606B2

公开(公告)日：2020-02-04

申请号：US15938101

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Won Kim ,  Hyun Goo Jun

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A vertical-type memory device and a manufacturing method thereof, the device including a substrate having a cell array region and a connection region; gate electrode layers stacked on the cell array region and the connection region of the substrate, the gate electrode layers forming a stepped structure in the connection region; a cell channel layer in the cell array region, the cell channel layer passing through the plurality of gate electrode layers; a dummy channel layer in the connection region, the dummy channel layer passing through at least one gate electrode layer of the plurality of gate electrode layers; a cell epitaxial layer disposed below the cell channel layer; and a dummy epitaxial layer disposed below the dummy channel layer, wherein the dummy epitaxial layer has a shape that is different from a shape of the cell epitaxial layer.

公开(公告)号：US10546874B2

公开(公告)日：2020-01-28

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: G11C8/00 ,  H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US10964720B2

公开(公告)日：2021-03-30

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  H01L27/11565 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  G11C7/14

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US09181170B2

公开(公告)日：2015-11-10

申请号：US14098154

申请日：2013-12-05

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jun Chwae ,  Nam Soo Park ,  Moo Ho Lee ,  Jong Won Kim

IPC: C07C51/347 ,  C07C51/377

CPC classification number: C07C51/347 ,  C07C51/377 ,  C07C59/01 ,  C07C57/04

Abstract: A method for preparing an unsaturated carboxylic acid comprising (a) preparing an aqueous solution comprising an ammonium salt of hydroxycarboxylic acid and a salt of inorganic acid; (b) contacting the aqueous solution with a cation exchange resin to prepare a conversion aqueous solution comprising a hydroxycarboxylic acid and an inorganic acid; and (c) dehydrating the hydroxycarboxylic acid using the inorganic acid as a catalyst is provided.

Abstract translation: 一种制备不饱和羧酸的方法，包括（a）制备包含羟基羧酸的铵盐和无机酸的盐的水溶液; （b）使所述水溶液与阳离子交换树脂接触以制备包含羟基羧酸和无机酸的转化水溶液; 和（c）使用无机酸作为催化剂使羟基羧酸脱水。

公开(公告)号：US20180350831A1

公开(公告)日：2018-12-06

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog EUN

IPC: H01L27/11582 ,  G11C11/4099 ,  G11C16/10 ,  G11C7/14 ,  H01L27/11526

CPC classification number: H01L27/11582 ,  G11C7/14 ,  G11C11/4099 ,  G11C16/107 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US09716104B2

公开(公告)日：2017-07-25

申请号：US14987835

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  HanMei Choi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11568

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US20140171681A1

公开(公告)日：2014-06-19

申请号：US14098154

申请日：2013-12-05

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jun CHWAE ,  Nam Soo Park ,  Moo Ho Lee ,  Jong Won Kim

IPC: C07C51/347

CPC classification number: C07C51/347 ,  C07C51/377 ,  C07C59/01 ,  C07C57/04

Abstract: A method for preparing an unsaturated carboxylic acid comprising (a) preparing an aqueous solution comprising an ammonium salt of hydroxycarboxylic acid and a salt of inorganic acid; (b) contacting the aqueous solution with a cation exchange resin to prepare a conversion aqueous solution comprising a hydroxycarboxylic acid and an inorganic acid; and (c) dehydrating the hydroxycarboxylic acid using the inorganic acid as a catalyst is provided.

Abstract translation: 一种制备不饱和羧酸的方法，包括（a）制备包含羟基羧酸的铵盐和无机酸的盐的水溶液; （b）使所述水溶液与阳离子交换树脂接触以制备包含羟基羧酸和无机酸的转化水溶液; 和（c）使用无机酸作为催化剂使羟基羧酸脱水。

公开(公告)号：US11296110B2

公开(公告)日：2022-04-05

申请号：US16797884

申请日：2020-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang Young Jung ,  Jong Won Kim ,  Young Hwan Son ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423

Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.

公开(公告)号：US10854631B2

公开(公告)日：2020-12-01

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.