公开(公告)号：US20240087976A1

公开(公告)日：2024-03-14

申请号：US18243437

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk Kim ,  Mina Choi

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/42 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/36 ,  H01L23/42 ,  H01L24/32 ,  H01L25/0652 ,  H10B80/00 ,  H01L24/16 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06589

Abstract: Provided is a semiconductor package including a first substrate, a first chip structure on the first substrate, the first chip structure including at least one chip, a heat dissipation member on the first chip structure, the heat dissipation member including a heat dissipation plate including a first surface facing the first chip structure and a second surface opposite to the first surface and a seed metal layer on the second surface of the heat dissipation plate, and a metal thermal interfacial material (TIM) on the seed metal layer.

公开(公告)号：US20230395459A1

公开(公告)日：2023-12-07

申请号：US18305726

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  Youngdeuk Kim ,  Mina Choi

IPC: H01L23/367 ,  H01L25/16 ,  H10B80/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes: a first semiconductor chip on a first package substrate; a second semiconductor chip on a second package substrate; an interposer between the first semiconductor chip and the second package substrate; and a heat dissipation layer on the interposer, wherein the first and second semiconductor chips are spaced apart from each other horizontally and do not overlap in a vertical direction, and wherein a first portion of the heat dissipation layer at least partially overlapping the first semiconductor chip in the vertical direction and a second portion of the heat dissipation layer at least partially overlapping the second semiconductor chip in the vertical direction are spaced apart from each other, and the first portion is positioned around an outer boundary of the second portion.

公开(公告)号：US11721604B2

公开(公告)日：2023-08-08

申请号：US16953745

申请日：2020-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo Choi ,  Seungduk Baek ,  Youngdeuk Kim

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/532 ,  H01L23/31 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06589

Abstract: Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.

公开(公告)号：US20230063886A1

公开(公告)日：2023-03-02

申请号：US17844395

申请日：2022-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Jo ,  Youngdeuk Kim ,  Jaechoon Kim ,  Taehwan Kim ,  Kyungsuk Oh

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of third semiconductor chips sequentially stacked on the second semiconductor chip, in which a horizontal width of each of the first semiconductor chip and the second semiconductor chip is greater than a horizontal width of each of the plurality of third semiconductor chips, and the first semiconductor chip and the second semiconductor chip are connected to each other through direct contact of a bonding pad.