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    Semiconductor package having molding member and heat dissipation member
    1.
    发明授权
    Semiconductor package having molding member and heat dissipation member 有权

    公开(公告)号：US11482507B2

    公开(公告)日：2022-10-25

    申请号：US16816593

    申请日：2020-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunchul Kim ,  Kyungsuk Oh ,  Taehun Kim ,  Pyoungwan Kim ,  Soohwan Lee

    IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00

    Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11101243B2

    公开(公告)日：2021-08-24

    申请号：US16680657

    申请日：2019-11-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongho Park ,  Kyungsuk Oh ,  Hyunki Kim ,  Yongkwan Lee ,  Sangsoo Kim ,  Seungkon Mok ,  Junyoung Oh ,  Changyoung Yoo

    IPC: H01L25/065 ,  H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

    Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

    Semiconductor package and method of manufacturing the same
    4.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US12199002B2

    公开(公告)日：2025-01-14

    申请号：US17736500

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehwan Kim ,  Kyungsuk Oh ,  Jaechoon Kim

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L25/04

    Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to the second through electrodes by bypassing the cool zone via the first heat redistribution through electrodes.

    Integrated circuit semiconductor device
    5.
    发明授权
    Integrated circuit semiconductor device 有权

    公开(公告)号：US12009303B2

    公开(公告)日：2024-06-11

    申请号：US17374713

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

    Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

    Semiconductor package
    7.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11631660B2

    公开(公告)日：2023-04-18

    申请号：US17243127

    申请日：2021-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

    Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE
    8.
    发明公开
    INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240290720A1

    公开(公告)日：2024-08-29

    申请号：US18660550

    申请日：2024-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

    Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

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