公开(公告)号：US12009303B2

公开(公告)日：2024-06-11

申请号：US17374713

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US20240290720A1

公开(公告)日：2024-08-29

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US20220130761A1

公开(公告)日：2022-04-28

申请号：US17374713

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/36 ,  H01L23/00

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US12237268B2

公开(公告)日：2025-02-25

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.