公开(公告)号：US10262935B2

公开(公告)日：2019-04-16

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju Kim ,  Su-A Kim ,  Soo-Young Kim ,  Min-Woo Won ,  Bok-Yeon Won ,  Ji-Suk Kwon ,  Young-Ho Kim ,  Ji-Hak Yu ,  Hyun-Chul Yoon ,  Seok-Jae Lee ,  Sang-Keun Han ,  Woong-Dai Kang ,  Hyuk-Joon Kwon ,  Bum-Jae Lee

IPC: H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L23/552 ,  G11C7/10 ,  G11C7/06

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US10163741B2

公开(公告)日：2018-12-25

申请号：US15677053

申请日：2017-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ho Kim ,  Ho-Sung Song ,  Jeong-Sik Nam ,  Kyoung-Min Kim ,  Tae-Hyeong Lee

IPC: G01R31/28 ,  H01L21/66 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.

公开(公告)号：US09223406B2

公开(公告)日：2015-12-29

申请号：US13964553

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beyong-Ho Yuu ,  Young-Ho Kim ,  Kyu-Hyuk Lee

IPC: G06F3/01 ,  G06F3/0488

CPC classification number: G06F3/017 ,  G06F3/04883 ,  G06F2203/04806

Abstract: A method and apparatus for zooming in or out and displaying a screen according a gesture of a user is provided. The method includes sensing gesture input, determining whether the gesture input corresponds to a predetermined pattern of a first semicircle or semi oval shape, and zooming in or out the image displayed on the screen and displaying a zoomed in or zoomed out image on a screen wherein the zoom ratio is in proportion to a radius of a first semicircle or a radius of a long or short axis of a first semi oval when the gesture input is the pattern of the first semicircle or semi oval shape.

Abstract translation: 提供了一种用于根据用户的手势放大或缩小并显示屏幕的方法和装置。 该方法包括感测手势输入，确定手势输入是否对应于第一半圆形或半椭圆形的预定图案，以及放大或缩小显示在屏幕上的图像，并在屏幕上显示放大或缩小图像，其中 当手势输入是第一半圆形或半椭圆形的图案时，变焦比与第一半圆的半径或第一半椭圆的长轴或短轴的半径成比例。

公开(公告)号：US11239175B2

公开(公告)日：2022-02-01

申请号：US16865470

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ho Kim ,  Hwan Pil Park ,  Sung-Chul Kim ,  Key-One Ahn

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38 ,  H01L23/31

Abstract: A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.