公开(公告)号：US10224109B2

公开(公告)日：2019-03-05

申请号：US15919155

申请日：2018-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Kim ,  Dong-chan Kim ,  Ji-sang Lee

IPC: G11C11/56 ,  G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

公开(公告)号：US20170069389A1

公开(公告)日：2017-03-09

申请号：US15251090

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-SOO PARK ,  Yoon Kim ,  Won-Bo Shim

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/349

Abstract: A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

Abstract translation: 如下提供擦除包括多个NAND串的非易失性存储器件的方法。 对每个字线施加第一电压用于相应的有效擦除执行时间。 对连接到每个字线的存储器单元执行相应的有效擦除执行时间的擦除操作。 在相应的有效擦除执行时间过去之后，对于相应的擦除禁止时间，在字线中的至少一些字线中的每一个上施加第二电压。 对于至少一些字线中的每一个，对应的有效擦除执行时间和相应的擦除禁止时间的总和基本上等于使用第一电压和第二电压高于第二电压的第二电压执行擦除操作的擦除间隔 第一电压。 字线堆叠在基板上。

公开(公告)号：US09824765B2

公开(公告)日：2017-11-21

申请号：US15251090

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Soo Park ,  Yoon Kim ,  Won-Bo Shim

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/349

Abstract: A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

公开(公告)号：US20180204621A1

公开(公告)日：2018-07-19

申请号：US15919155

申请日：2018-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Kim ,  Dong-chan Kim ,  Ji-sang Lee

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/349

Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.