公开(公告)号：US09928799B2

公开(公告)日：2018-03-27

申请号：US14851265

申请日：2015-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HaJun Lee ,  Jin-Han Kim ,  Junho Song ,  SeongJong Yoo ,  Yeonwoo Jung ,  Yong-Hun Kim ,  Keemoon Chun

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

公开(公告)号：US09265125B2

公开(公告)日：2016-02-16

申请号：US13799795

申请日：2013-03-13

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Yong-Hun Kim ,  Hyungtae Kim

IPC: H05B37/02 ,  G09G3/36

CPC classification number: H05B37/02 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2320/0276 ,  G09G2320/0673

Abstract: A gamma voltage generating circuit includes a gamma voltage distribution unit configured to divide a reference voltage to generate a plurality of initial gamma reference voltages, and a gamma voltage selection unit configured to generate gamma reference voltages by selecting first gamma reference voltages, corresponding to a first color pixel, from among the plurality of initial gamma reference voltages and second gamma reference voltages, corresponding to a second color pixel, from among the plurality of initial gamma reference voltages. Herein, an output part of initial gamma reference voltages selected in common as the first and second gamma reference voltages is shared with input parts of the first and second gamma reference voltages.

Abstract translation: 伽玛电压发生电路包括：伽马电压分配单元，被配置为分配参考电压以产生多个初始伽马参考电压;伽马电压选择单元，被配置为通过选择第一伽马参考电压来产生伽马参考电压，所述伽马参考电压对应于第一 从所述多个初始伽马参考电压之中的多个初始伽马参考电压和对应于第二彩色像​​素的第二伽马参考电压的颜色像素。 这里，作为第一和第二伽马参考电压共同选择的初始伽马参考电压的输出部分与第一和第二伽马参考电压的输入部分共享。

公开(公告)号：US10186219B2

公开(公告)日：2019-01-22

申请号：US15187920

申请日：2016-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hun Kim ,  Hyunsang Park ,  Kyungchun Kim ,  Jae-Bum Lee

IPC: G09G3/36 ,  H03M1/06 ,  H03M1/66

Abstract: A digital-to-analog converter includes an amplifier including at least two input terminals corresponding to a non-inverting input terminal; and a chopping unit performing a chopping operation between voltages provided to the at least two input terminals corresponding to the non-inverting input terminal. The digital-to-analog converter has an X+Y bit structure and removes an offset by performing an interpolation chopping operation and/or a main buffer chopping operation at the same time. The digital-to-analog structure can be embodied in a small area and can process high bit image data.

公开(公告)号：US10157566B2

公开(公告)日：2018-12-18

申请号：US15446542

申请日：2017-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hun Kim ,  Hyun-Sang Park

IPC: G09G3/20 ,  G09G3/36

Abstract: A display driving device includes a timing controller, a power management integrated circuit, and a column driver. The timing controller generates image data including a plurality of pixel data, and generates a power saving signal based on magnitudes of the plurality of pixel data included in the image data. The power management integrated circuit generates a drive voltage having a voltage level that is varied based on the power saving signal. The column driver receives the image data generated by the timing controller, and generates a plurality of output voltages corresponding to the plurality of pixel data included in the image data based on the drive voltage.

公开(公告)号：US09628071B2

公开(公告)日：2017-04-18

申请号：US14228865

申请日：2014-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： EunJong Jang ,  Yong-Hun Kim ,  Myoungsik Suh ,  Jae-Bum Lee ,  SooJin Park

IPC: G09G5/00 ,  H03K17/22 ,  G06F1/24 ,  G09G3/20

CPC classification number: H03K17/223 ,  G06F1/24 ,  G09G3/20 ,  G09G5/003 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2330/026

Abstract: A power-on reset circuit includes a voltage detector unit to output an electrical signal in response to a power supply voltage received from a power supply terminal, an inverter to output a reset signal according to a level of the electrical signal from the voltage detector unit, a first switch unit to be turned on or off in response to the reset signal from the inverter; a first discharge unit to discharge the electrical signal in response to the power supply voltage from the first switch unit, a second switch unit to be turned on according to a start pulse signal from an external device and to receive the power supply voltage from the power supply terminal, and a second discharge unit to discharge the electrical signal in response to the power supply voltage from the second switch.

公开(公告)号：US11967287B2

公开(公告)日：2024-04-23

申请号：US17950599

申请日：2022-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghan Lee ,  Yong-Hun Kim

IPC: G09G3/3275 ,  G09G3/20

CPC classification number: G09G3/3275 ,  G09G3/2007 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/023 ,  G09G2330/028

Abstract: A column driver integrated circuit (IC) which drives a first group of pixel lines connected to a first group of pixels included in a display panel, and a second group of pixel lines connected to a second group of pixels included in the display panel, the column driver IC including: a master gray scale voltage generation circuit configured to divide a reference voltage to generate tap voltages, and to generate a first low-power mode gray scale voltage based on at least one of the tap voltages; and a first low-power mode amplifier configured to drive the first group of pixel lines based on the first low-power mode gray scale voltage.

公开(公告)号：US10649849B2

公开(公告)日：2020-05-12

申请号：US15938092

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hun Kim ,  Su-Yeon Doo ,  Dong-Seok Kang ,  Hye-Jung Kwon ,  Young-Ju Kim

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/10 ,  H03K3/84 ,  H03K3/03

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

公开(公告)号：US20160093237A1

公开(公告)日：2016-03-31

申请号：US14851265

申请日：2015-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： HaJun LEE ,  Jin-Han Kim ,  Junho Song ,  SeongJong Yoo ,  Yeonwoo Jung ,  Yong-Hun Kim ,  Keemoon Chun

IPC: G09G3/20

CPC classification number: G09G3/3688 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

Abstract translation: 提供了一种源驱动器电路，其包括多个数字多扩展（以下称为“DMS”）块，其被配置为生成DMS信号，用于控制要从多个数据传输到显示面板的数据信号的输出定时 时钟被延迟到另一个参考周期。 每个DMS块包括多个子块。 每个子块包括使能信号发生器和延迟单元。 使能信号发生器产生使能信号，用于使用从多个时钟中选择的时钟输出DMS信号的目标DMS信号。 延迟单元延迟DMS信号，使得DMS信号被顺序地延迟参考周期。

公开(公告)号：US20150269911A1

公开(公告)日：2015-09-24

申请号：US14581356

申请日：2014-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungpil CHOI ,  Hyungwoo Yu ,  Narae Shin ,  Kijoon Kim ,  Yong-Hun Kim ,  SooJin Park ,  Myoungsik Suh ,  Jae-Bum Lee ,  EunJong Jang

IPC: G09G5/18 ,  H01L23/50 ,  H01L23/522 ,  H01L23/00 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L23/50 ,  G09G5/005 ,  G09G2300/0404 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2340/0435 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/06153 ,  H01L2224/08237

Abstract: Provided is a chip on film package including an integrated circuit chip and a film. The integrated circuit chip includes one or more first output pads along a first longer side, and one or more second output pads along a second longer side which faces the first longer side. The film includes a lower film, a plurality of film conducting wires on one face of the lower film, and an upper film on the plurality of film conducting wires. Each of the plurality of film conducting wires may be spaced apart from an adjacent film conducting wire. The first output pads and the second output pads are respectively connected to the plurality of film conducting wires electrically. The plurality of film conducting wires is a single layer between the upper film and the lower film.

Abstract translation: 提供了包括集成电路芯片和薄膜的薄膜封装芯片。 集成电路芯片包括沿着第一长边的一个或多个第一输出焊盘，以及沿着第二长边的面向第一长边的一个或多个第二输出焊盘。 该膜包括下膜，在下膜的一个面上的多个膜导电丝和多个膜导电线上的上膜。 多个膜导电线中的每一个可以与相邻的膜导电线分开。 第一输出焊盘和第二输出焊盘分别电连接到多个膜导电线。 多个膜导电线是上膜和下膜之间的单层。