公开(公告)号：US20150269911A1

公开(公告)日：2015-09-24

申请号：US14581356

申请日：2014-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungpil CHOI ,  Hyungwoo Yu ,  Narae Shin ,  Kijoon Kim ,  Yong-Hun Kim ,  SooJin Park ,  Myoungsik Suh ,  Jae-Bum Lee ,  EunJong Jang

IPC: G09G5/18 ,  H01L23/50 ,  H01L23/522 ,  H01L23/00 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L23/50 ,  G09G5/005 ,  G09G2300/0404 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2340/0435 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/06153 ,  H01L2224/08237

Abstract: Provided is a chip on film package including an integrated circuit chip and a film. The integrated circuit chip includes one or more first output pads along a first longer side, and one or more second output pads along a second longer side which faces the first longer side. The film includes a lower film, a plurality of film conducting wires on one face of the lower film, and an upper film on the plurality of film conducting wires. Each of the plurality of film conducting wires may be spaced apart from an adjacent film conducting wire. The first output pads and the second output pads are respectively connected to the plurality of film conducting wires electrically. The plurality of film conducting wires is a single layer between the upper film and the lower film.

Abstract translation: 提供了包括集成电路芯片和薄膜的薄膜封装芯片。 集成电路芯片包括沿着第一长边的一个或多个第一输出焊盘，以及沿着第二长边的面向第一长边的一个或多个第二输出焊盘。 该膜包括下膜，在下膜的一个面上的多个膜导电丝和多个膜导电线上的上膜。 多个膜导电线中的每一个可以与相邻的膜导电线分开。 第一输出焊盘和第二输出焊盘分别电连接到多个膜导电线。 多个膜导电线是上膜和下膜之间的单层。