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1.发明公开公开(公告)号：US20230163778A1
公开(公告)日：2023-05-25
申请号：US18057969
申请日：2022-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young Sea CHO , Wan KIM , Yong LIM
CPC classification number: H03M1/38 , H03M1/1245
Abstract: An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.
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公开(公告)号：US20140145067A1
公开(公告)日：2014-05-29
申请号：US14084705
申请日：2013-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung Ho SUH , Yu Jin PARK , Jin Ho SEO , Kwi Sung YOO , Seung Hyun LIM , Seog Heon HAM , Kyoung Min KOH , Han YANG , Jae Cheol YUN , Yong LIM , Jae Jin JUNG
IPC: H04N5/378
CPC classification number: H04N5/378 , H04N5/3742
Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.
Abstract translation: 图像传感器包括像素阵列的多列之中的第一列对和第二列对，模数转换器对以及被配置为将第一列对与模拟 - 数字转换器对连接的开关布置电路， 数字转换器对响应于第一开关控制信号，使得在单个访问时间期间读取像素阵列中的多行中的两行。
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公开(公告)号：US20210336586A1
公开(公告)日：2021-10-28
申请号：US17173943
申请日：2021-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong Mi LEE , Yong LIM , Chilun LO
Abstract: A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.
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公开(公告)号：US20230231571A1
公开(公告)日：2023-07-20
申请号：US18150636
申请日：2023-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hoon LEE , Yong LIM
Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.
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Patent Agency Ranking
公开(公告)号：US20230223906A1
公开(公告)日：2023-07-13
申请号：US17979148
申请日：2022-11-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hoon LEE , Yong LIM
IPC: H03F3/45
CPC classification number: H03F3/45269 , H03F2200/451
Abstract: An amplifier and an electronic system including the same are provided. An amplifier includes a first NMOS transistor configured to receive a first input, a second NMOS transistor configured to receive a second input, the second NMOS transistor including a source connected to a source of the first NMOS transistor, a first resistor including a first end connected to a drain of the first NMOS transistor and a second end connected to a first output, a second resistor including a first end connected to a drain of the second NMOS transistor, and a second end connected to a second output, and the amplifier is configured to generate the first output and the second output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.
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公开(公告)号：US20250038711A1
公开(公告)日：2025-01-30
申请号：US18765598
申请日：2024-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong LIM , Jaehoon LEE
Abstract: An amplifier includes a first stage amplifier circuit configured to receive an input voltage and a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branching off from an output terminal of the first stage amplifier circuit and each including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit may be configured to sample a voltage corresponding to a first bias current corresponding to the second stage and a voltage corresponding to a second bias current corresponding to the third stage in a first phase, and bias the second stage with the voltage corresponding to the first bias current and bias the third stage with the voltage corresponding to the second bias current in a second phase.
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7.发明公开公开(公告)号：US20230221747A1
公开(公告)日：2023-07-13
申请号：US18149278
申请日：2023-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon LEE , Yong LIM , Seunghyun OH
Abstract: A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.
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公开(公告)号：US20220407538A1
公开(公告)日：2022-12-22
申请号：US17705776
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon LEE , Yong LIM , Seunghyun OH
Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.
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公开(公告)号：US20220239310A1
公开(公告)日：2022-07-28
申请号：US17564668
申请日：2021-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong LIM , Jaehoon LEE
Abstract: An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.
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