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    G-LDPC DECODER AND G-LDPC DECODING METHOD
    1.
    发明公开
    G-LDPC DECODER AND G-LDPC DECODING METHOD 审中-公开

    公开(公告)号：US20240106462A1

    公开(公告)日：2024-03-28

    申请号：US18141103

    申请日：2023-04-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dae-Yeol Yang ,  BOHWAN JUN ,  HONG RAK SON ,  GEUNYEONG YU ,  YOUNGJUN HWANG

    IPC分类号： H03M13/11 ,  H03M13/00

    CPC分类号： H03M13/1111 ,  H03M13/611

    摘要： a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.

    STORAGE DEVICE THAT PERFORMS STATE SHAPING OF DATA
    2.
    发明申请
    STORAGE DEVICE THAT PERFORMS STATE SHAPING OF DATA 有权

    公开(公告)号：US20210026734A1

    公开(公告)日：2021-01-28

    申请号：US16835721

    申请日：2020-03-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： YOUNGJUN HWANG ,  DONG-MIN SHIN ,  CHANGKYU SEOL ,  JAEYONG SON ,  HONG RAK SON

    IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/26

    摘要： A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

    METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PERFORMING THE SAME
    3.
    发明公开
    METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PERFORMING THE SAME 审中-公开

    公开(公告)号：US20230187011A1

    公开(公告)日：2023-06-15

    申请号：US17854638

    申请日：2022-06-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KANGSEOK LEE ,  GEUNYEONG YU ,  SEONGHYEOG CHOI ,  HONGRAK SON ,  YOUNGJUN HWANG

    IPC分类号： G11C29/52 ,  G11C29/02

    CPC分类号： G11C29/52 ,  G11C29/021 ,  G11C29/022

    摘要： In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.