DEVICE AND METHOD FOR PROCESSING DATA USING LOGICAL INFORMATION AND PHYSICAL INFORMATION
    1.
    发明申请
    DEVICE AND METHOD FOR PROCESSING DATA USING LOGICAL INFORMATION AND PHYSICAL INFORMATION 有权
    使用逻辑信息和物理信息处理数据的装置和方法

    公开(公告)号:US20150261606A1

    公开(公告)日:2015-09-17

    申请号:US14641649

    申请日:2015-03-09

    Abstract: A method of operating a data storage device according to an exemplary embodiment of the present inventive concepts includes generating at least one pseudo noise (PN) sequence using logical information and physical information for the data storage device, and converting first data into second data using the at least one PN sequence. Generating the at least one PN sequence includes generating a random seed based on the logical information and the physical information, and generating the at least one PN sequence using the random seed. The logical information may be a logical page address for the data storage device, and the physical information may be a physical page address for the data storage device.

    Abstract translation: 根据本发明构思的示例性实施例的操作数据存储设备的方法包括使用数据存储设备的逻辑信息和物理信息来生成至少一个伪噪声(PN)序列,并且使用 至少一个PN序列。 生成所述至少一个PN序列包括基于所述逻辑信息和所述物理信息生成随机种子,以及使用所述随机种子生成所述至少一个PN序列。 逻辑信息可以是数据存储设备的逻辑页面地址,并且物理信息可以是数据存储设备的物理页面地址。

    METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PERFORMING THE SAME

    公开(公告)号:US20230187011A1

    公开(公告)日:2023-06-15

    申请号:US17854638

    申请日:2022-06-30

    CPC classification number: G11C29/52 G11C29/021 G11C29/022

    Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.

    MEMORY SYSTEM AND ENCRYPTION METHOD IN MEMORY SYSTEM
    3.
    发明申请
    MEMORY SYSTEM AND ENCRYPTION METHOD IN MEMORY SYSTEM 审中-公开
    记忆系统中的记忆系统和加密方法

    公开(公告)号:US20140032935A1

    公开(公告)日:2014-01-30

    申请号:US13839156

    申请日:2013-03-15

    CPC classification number: G06F21/602 G06F21/6218

    Abstract: An encryption method used in the memory system includes; generating a private key using physical unique identification (PUID) information of a nonvolatile memory device, encrypting data using the private key, and then programming the encrypted data in the nonvolatile memory device.

    Abstract translation: 在存储器系统中使用的加密方法包括: 使用非易失性存储器件的物理唯一识别(PUID)信息生成私钥,使用私钥对数据进行加密,然后对非易失性存储器件中的加密数据进行编程。

    STACKED NEUROMORPHIC DEVICES AND NEUROMORPHIC COMPUTING SYSTEMS

    公开(公告)号:US20210125045A1

    公开(公告)日:2021-04-29

    申请号:US16854942

    申请日:2020-04-22

    Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

    HOMOMORPHIC ENCRYPTION DEVICE AND OPERATING METHOD THEREOF

    公开(公告)号:US20220094521A1

    公开(公告)日:2022-03-24

    申请号:US17343318

    申请日:2021-06-09

    Abstract: An encryption device includes: a parameter generating circuit configured to generate an encryption parameter including a number of initial valid bits based on an operation scenario; an encryption circuit configured to generate a cipher text by encrypting a plain text received from the outside, based on the encryption parameter; an operation circuit configured to generate a final cipher text by performing a plurality of operations on the cipher text according to the operation scenario and tag, to the final cipher text, history information of the operations performed on the final cipher text; and a decryption circuit configured to generate a decrypted plain text by decrypting the final cipher text and output a number of reliable bits of the decrypted plain text based on the history information.

    HOMOMORPHIC ENCRYPTION DEVICE AND CIPHERTEXT ARITHMETIC METHOD THEREOF

    公开(公告)号:US20210376996A1

    公开(公告)日:2021-12-02

    申请号:US17126935

    申请日:2020-12-18

    Abstract: A homomorphic encryption device includes: a recryption parameter generating circuit, a recryption circuit, and an arithmetic circuit. The recryption parameter generating circuit is configured to generate a recryption parameter including a plurality of recryption levels respectively for a plurality of ciphertexts based on an arithmetic scenario including information about an arithmetic schedule between the plurality of ciphertexts. The recryption circuit is configured to generate a plurality of recrypted ciphertexts by recrypting each of the plurality of ciphertexts to a corresponding recryption level based on the recryption parameter. The arithmetic circuit is configured to output an arithmetic result by performing operations by using the plurality of recrypted ciphertexts, according to the arithmetic scenario.

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