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公开(公告)号：US20230187011A1
公开(公告)日：2023-06-15
申请号：US17854638
申请日：2022-06-30
发明人： KANGSEOK LEE , GEUNYEONG YU , SEONGHYEOG CHOI , HONGRAK SON , YOUNGJUN HWANG
CPC分类号： G11C29/52 , G11C29/021 , G11C29/022
摘要： In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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公开(公告)号：US20190188078A1
公开(公告)日：2019-06-20
申请号：US16057855
申请日：2018-08-08
发明人： GEUNYEONG YU , BOHWAN JUN , KIJUN LEE , JUNJIN KONG , HONG-RAK SON
CPC分类号： G06F11/1076 , H03M13/1105 , H03M13/1154 , H03M13/3972 , H03M13/616
摘要： A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.
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公开(公告)号：US20240106462A1
公开(公告)日：2024-03-28
申请号：US18141103
申请日：2023-04-28
发明人： Dae-Yeol Yang , BOHWAN JUN , HONG RAK SON , GEUNYEONG YU , YOUNGJUN HWANG
CPC分类号： H03M13/1111 , H03M13/611
摘要： a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.
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公开(公告)号：US20210125045A1
公开(公告)日：2021-04-29
申请号：US16854942
申请日：2020-04-22
发明人： JAEHUN JANG , HONGRAK SON , CHANGYU SEOL , GEUNYEONG YU , CHANHO YOON , PILSANG YOON
IPC分类号： G06N3/063 , G06N3/04 , H01L25/065 , H01L25/18
摘要： A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.
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