公开(公告)号：US09252123B2

公开(公告)日：2016-02-02

申请号：US14505802

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/85 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4847 ,  H01L2224/48992 ,  H01L2224/4941 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8503 ,  H01L2224/85951 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract translation: 多芯片封装可以包括第一半导体芯片，第二半导体芯片，第一螺柱凸块，第一钉头结合凸块，第二凸柱凸块和第一导线。 第一半导体芯片可以具有第一接合焊盘。 第二半导体芯片可以堆叠在第一半导体芯片上，使得第一焊盘保持暴露。 第二半导体芯片可以具有第二接合焊盘。 可以在第一接合焊盘上形成第一螺柱凸块。 第一钉头结合凸块可以形成在第一凸起凸起上，其中一个第一导线形成在两者之间。 可以在第二接合焊盘上形成第二螺柱凸块，其中第一导线的另一端形成在两者之间。 可以在每个引线接合工艺上执行电连接测试。

公开(公告)号：US10903177B2

公开(公告)日：2021-01-26

申请号：US16511825

申请日：2019-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-Jin Yoo ,  Hong-Sub Joo ,  Won-Gil Han

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/00 ,  H01L23/60 ,  H01L21/56 ,  H01L25/18 ,  H01L23/31

Abstract: In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

公开(公告)号：US10784244B2

公开(公告)日：2020-09-22

申请号：US16177968

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Seung-Lo Lee ,  Yong-Je Lee ,  Sung-Il Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

公开(公告)号：US10679972B2

公开(公告)日：2020-06-09

申请号：US16193318

申请日：2018-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Gil Han ,  Byong-Joo Kim ,  Yong-Je Lee ,  Jae-Heung Lee ,  Seung-Weon Ha

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

公开(公告)号：US20190259742A1

公开(公告)日：2019-08-22

申请号：US16177968

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Seung-Lo Lee ,  Yong-je Lee ,  Sung-Il Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

公开(公告)号：US10147706B2

公开(公告)日：2018-12-04

申请号：US15623891

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Gil Han ,  Byong-Joo Kim ,  Yong-Je Lee ,  Jae-Heung Lee ,  Seung-Weon Ha

IPC: H01L25/065 ,  H01L23/00

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

公开(公告)号：US11594500B2

公开(公告)日：2023-02-28

申请号：US17132880

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-Jin Yoo ,  Hong-Sub Joo ,  Won-Gil Han

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/60 ,  H01L21/56 ,  H01L25/18 ,  H01L23/31

Abstract: In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

公开(公告)号：US10658326B2

公开(公告)日：2020-05-19

申请号：US15616525

申请日：2017-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Gil Han ,  Sangho An ,  Yong Je Lee ,  Jae Heung Lee ,  Seungweon Ha

IPC: H01L23/00 ,  H01L25/065

Abstract: A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

公开(公告)号：US09384105B2

公开(公告)日：2016-07-05

申请号：US14185447

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Kim ,  Yean-Sang You ,  Won-Gil Han ,  Ho-Am Kim ,  Byong-Joo Kim ,  Do-Hoon Lee

IPC: G06F11/00 ,  G06F11/26 ,  G01R31/04 ,  G01R31/02

CPC classification number: G06F11/26 ,  G01R31/025 ,  G01R31/04 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.

Abstract translation: 在线接合机中检测运算算法的故障的方法中，可以基于设计数据设定相关于引线键合机的各运算算法的各个结合参数，该设计数据包括关于连接在半导体芯片 半导体封装。 可以使用可以输入设计数据的引线接合机来形成实际的半导体封装的实际导线。 可以获得关于可形成实际导线的引线接合机的实际操作算法的实际数据。 实际数据可以与各自的绑定参数进行比较，以检测引线接合机的操作算法的故障。 因此，可以预先防止由引线接合机形成异常导电线。

公开(公告)号：US20140359372A1

公开(公告)日：2014-12-04

申请号：US14185447

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Kim ,  Yean-Sang You ,  Won-Gil Han ,  Ho-Am Kim ,  Byong-Joo Kim ,  Do-Hoon Lee

IPC: G05B23/02

CPC classification number: G06F11/26 ,  G01R31/025 ,  G01R31/04 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.

Abstract translation: 在线接合机中检测运算算法的故障的方法中，可以基于设计数据设定相关于引线键合机的各运算算法的各个结合参数，该设计数据包括关于连接在半导体芯片 半导体封装。 可以使用可以输入设计数据的引线接合机来形成实际的半导体封装的实际导线。 可以获得关于可形成实际导线的引线接合机的实际操作算法的实际数据。 实际数据可以与各自的绑定参数进行比较，以检测引线接合机的操作算法的故障。 因此，可以预先防止由引线接合机形成异常导电线。