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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230352297A1

    公开(公告)日：2023-11-02

    申请号：US18183571

    申请日：2023-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yurim KIM ,  Teawon Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

    IPC: H01L21/02

    CPC classification number: H01L21/02194 ,  H01L21/02205

    Abstract: A method of manufacturing a semiconductor device including providing a first precursor on a substrate to adsorb a first element of the first precursor onto a first region of the substrate, providing a second precursor on the substrate to adsorb a second element of the second precursor onto a second region of the substrate, the second region being different from the first region, and providing a reactant including oxygen on the substrate to form an oxide semiconductor layer including the first element of the first precursor, the second element of the second precursor, and the oxygen of the reactant may be provided.

    SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240074148A1

    公开(公告)日：2024-02-29

    申请号：US18230916

    申请日：2023-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/05 ,  H10B12/50

    Abstract: A semiconductor device includes a plurality of bit lines arranged on a substrate and extending in a first horizontal direction, a mold insulating layer arranged on the bit lines and including a plurality of openings extending in a second horizontal direction, respectively, a plurality of channel layers respectively arranged on the bit lines and including a first vertical extension portion, in each opening of the mold insulating layer, a plurality of passivation layers respectively arranged on each vertical extension portion, a gate insulating layer arranged to face each vertical extension portion with each passivation layer therebetween, and a plurality of word lines extending in the second horizontal direction on the gate insulating layer and including first word lines respectively arranged on a first sidewall of each opening of the mold insulating layer and second word lines respectively arranged on a second sidewall of each opening of the mold insulating layer.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12213304B2

    公开(公告)日：2025-01-28

    申请号：US17825441

    申请日：2022-05-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Teawon Kim ,  Yurim Kim ,  Seohee Park ,  Kong-Soo Lee ,  Yong Suk Tak

    IPC: H01L27/108 ,  H10B12/00

    Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

    FIELD EFFECT TRANSISTOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME
    5.
    发明公开
    FIELD EFFECT TRANSISTOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240079498A1

    公开(公告)日：2024-03-07

    申请号：US18236623

    申请日：2023-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak ,  Seungwoo Jang

    IPC: H01L29/786 ,  H10B12/00

    CPC classification number: H01L29/7869 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

    Abstract: Provided is a field effect transistor including a gate electrode layer, an oxide semiconductor layer including gallium (Ga) and at least one metal element selected from indium (In) and zinc (Zn), and a dielectric layer between the gate electrode layer and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a sub semiconductor layer in contact with the dielectric layer and a main semiconductor layer spaced apart from the dielectric layer with the sub semiconductor layer therebetween, the sub semiconductor layer has a first Ga content, and the first Ga content of the sub semiconductor layer is greater than contents of other metal elements included in the sub semiconductor layer and decreases as a distance from an interface of the sub semiconductor layer in contact with the dielectric layer increases.

    SEMICONDUCTOR DEVICE INCLUDING SPACER STRUCTURE HAVING AIR GAP
    6.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING SPACER STRUCTURE HAVING AIR GAP 审中-公开

    公开(公告)号：US20240215225A1

    公开(公告)日：2024-06-27

    申请号：US18391835

    申请日：2023-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Teawon Kim ,  Seohee Park ,  Yongsuk Tak ,  Minkyung Kang ,  Joonnyung Heo

    IPC: H10B12/00 ,  H01L21/764

    CPC classification number: H10B12/482 ,  H01L21/764 ,  H10B12/0335 ,  H10B12/315

    Abstract: A semiconductor device includes a line structure on the lower structure and including a conductive pattern and an insulating capping pattern on the conductive pattern, a contact structure including a lower portion adjacent to a side surface of the line structure and an upper portion on the lower portion, a spacer structure between a side surface of the lower portion of the contact structure and the side surface of the line structure, an insulating separation pattern on the spacer structure, and a protective layer between the upper portion of the contact structure and the insulating separation pattern. The spacer structure includes an internal spacer, an external spacer, and an air gap between the internal spacer and the external spacer. Regions of the internal spacer and the external spacer exposed by the air gap include an oxide. The insulating separation pattern seals at least a portion of an upper portion of the air gap.

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