公开(公告)号：US20240074148A1

公开(公告)日：2024-02-29

申请号：US18230916

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor device includes a plurality of bit lines arranged on a substrate and extending in a first horizontal direction, a mold insulating layer arranged on the bit lines and including a plurality of openings extending in a second horizontal direction, respectively, a plurality of channel layers respectively arranged on the bit lines and including a first vertical extension portion, in each opening of the mold insulating layer, a plurality of passivation layers respectively arranged on each vertical extension portion, a gate insulating layer arranged to face each vertical extension portion with each passivation layer therebetween, and a plurality of word lines extending in the second horizontal direction on the gate insulating layer and including first word lines respectively arranged on a first sidewall of each opening of the mold insulating layer and second word lines respectively arranged on a second sidewall of each opening of the mold insulating layer.

公开(公告)号：US20240276711A1

公开(公告)日：2024-08-15

申请号：US18380848

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yurim Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: The semiconductor device may include a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a first channel contacting an upper surface of the bit line and the sidewall of the gate insulation pattern and a contact plug contacting an upper surface of the first channel. The first channel may include a spinel IGZO.

公开(公告)号：US12213304B2

公开(公告)日：2025-01-28

申请号：US17825441

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon Kim ,  Yurim Kim ,  Seohee Park ,  Kong-Soo Lee ,  Yong Suk Tak

IPC: H01L27/108 ,  H10B12/00

Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

公开(公告)号：US20240414925A1

公开(公告)日：2024-12-12

申请号：US18436574

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Inventor： Seunghee Lee ,  Jin-Seong Park ,  Jihyun Kho ,  Dong-Gyu Kim ,  Yurim Kim ,  Yong-Suk Tak

IPC: H10B53/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device has, in a gate insulating layer, in an XPS spectrum of O 1s obtained by an X-ray photoelectron spectroscopy (XPS) using a monochromatic aluminum Kα (1486.6 eV) source, a ratio (%) of an Al—O peak observed in a binding energy of about 530.3 eV to about 531.6 eV to all peaks of greater than or equal to about 80%.

公开(公告)号：US20240079498A1

公开(公告)日：2024-03-07

申请号：US18236623

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak ,  Seungwoo Jang

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a field effect transistor including a gate electrode layer, an oxide semiconductor layer including gallium (Ga) and at least one metal element selected from indium (In) and zinc (Zn), and a dielectric layer between the gate electrode layer and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a sub semiconductor layer in contact with the dielectric layer and a main semiconductor layer spaced apart from the dielectric layer with the sub semiconductor layer therebetween, the sub semiconductor layer has a first Ga content, and the first Ga content of the sub semiconductor layer is greater than contents of other metal elements included in the sub semiconductor layer and decreases as a distance from an interface of the sub semiconductor layer in contact with the dielectric layer increases.