公开(公告)号：US20240414925A1

公开(公告)日：2024-12-12

申请号：US18436574

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Inventor： Seunghee Lee ,  Jin-Seong Park ,  Jihyun Kho ,  Dong-Gyu Kim ,  Yurim Kim ,  Yong-Suk Tak

IPC: H10B53/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device has, in a gate insulating layer, in an XPS spectrum of O 1s obtained by an X-ray photoelectron spectroscopy (XPS) using a monochromatic aluminum Kα (1486.6 eV) source, a ratio (%) of an Al—O peak observed in a binding energy of about 530.3 eV to about 531.6 eV to all peaks of greater than or equal to about 80%.

公开(公告)号：US20240079498A1

公开(公告)日：2024-03-07

申请号：US18236623

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak ,  Seungwoo Jang

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a field effect transistor including a gate electrode layer, an oxide semiconductor layer including gallium (Ga) and at least one metal element selected from indium (In) and zinc (Zn), and a dielectric layer between the gate electrode layer and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a sub semiconductor layer in contact with the dielectric layer and a main semiconductor layer spaced apart from the dielectric layer with the sub semiconductor layer therebetween, the sub semiconductor layer has a first Ga content, and the first Ga content of the sub semiconductor layer is greater than contents of other metal elements included in the sub semiconductor layer and decreases as a distance from an interface of the sub semiconductor layer in contact with the dielectric layer increases.

公开(公告)号：US20230352297A1

公开(公告)日：2023-11-02

申请号：US18183571

申请日：2023-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yurim KIM ,  Teawon Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

IPC: H01L21/02

CPC classification number: H01L21/02194 ,  H01L21/02205

Abstract: A method of manufacturing a semiconductor device including providing a first precursor on a substrate to adsorb a first element of the first precursor onto a first region of the substrate, providing a second precursor on the substrate to adsorb a second element of the second precursor onto a second region of the substrate, the second region being different from the first region, and providing a reactant including oxygen on the substrate to form an oxide semiconductor layer including the first element of the first precursor, the second element of the second precursor, and the oxygen of the reactant may be provided.

公开(公告)号：US09253471B2

公开(公告)日：2016-02-02

申请号：US13767521

申请日：2013-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanghyuk Bae ,  Kyu-Min Kyung ,  Tae-Chan Kim ,  Seunghee Lee

IPC: H04N13/02 ,  H04N5/12 ,  G01S17/10 ,  G01S17/87 ,  G01S17/89 ,  H04N5/04

CPC classification number: H04N13/271 ,  G01S17/107 ,  G01S17/87 ,  G01S17/89 ,  H04N5/04 ,  H04N5/123

Abstract: A depth camera includes a sensor unit receiving a reflected light and in response thereto outputting an electrical sensing signal; and a synchronization information calculation unit calculating a performance index with reference to the sensing signal, and with reference to the performance index, generating synchronization information for synchronizing a demodulation clock for sensing the received reflected light. The sensor unit adjusts the frequency and/or phase of the demodulation clock with reference to the synchronization information.

Abstract translation: 深度照相机包括接收反射光的传感器单元，并且响应于此输出电感测信号; 以及同步信息计算单元，参考感测信号来计算性能指标，并且参考性能指标，产生用于同步用于感测所接收的反射光的解调时钟的同步信息。 传感器单元参照同步信息调整解调时钟的频率和/或相位。

公开(公告)号：US20240280917A1

公开(公告)日：2024-08-22

申请号：US18468505

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Dohyun ,  Youngduk Suh ,  Sungwook Kang ,  Sanggon Shin ,  Seunghee Lee ,  Jinwook Jung

IPC: G03F7/00

CPC classification number: G03F7/70925

Abstract: An apparatus for cleaning an EUV light creation chamber may include a cleaning module, a first movement module and a second movement module. The first movement module may support the cleaning module in the EUV light creation chamber along a first direction. The second movement module may support the first movement module on a surface of the EUV light creation chamber at a position along a second direction perpendicular to the first direction.

公开(公告)号：US20240276711A1

公开(公告)日：2024-08-15

申请号：US18380848

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yurim Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: The semiconductor device may include a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a first channel contacting an upper surface of the bit line and the sidewall of the gate insulation pattern and a contact plug contacting an upper surface of the first channel. The first channel may include a spinel IGZO.

公开(公告)号：US20240074148A1

公开(公告)日：2024-02-29

申请号：US18230916

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor device includes a plurality of bit lines arranged on a substrate and extending in a first horizontal direction, a mold insulating layer arranged on the bit lines and including a plurality of openings extending in a second horizontal direction, respectively, a plurality of channel layers respectively arranged on the bit lines and including a first vertical extension portion, in each opening of the mold insulating layer, a plurality of passivation layers respectively arranged on each vertical extension portion, a gate insulating layer arranged to face each vertical extension portion with each passivation layer therebetween, and a plurality of word lines extending in the second horizontal direction on the gate insulating layer and including first word lines respectively arranged on a first sidewall of each opening of the mold insulating layer and second word lines respectively arranged on a second sidewall of each opening of the mold insulating layer.