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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240203475A1

    公开(公告)日：2024-06-20

    申请号：US18593937

    申请日：2024-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230021622A1

    公开(公告)日：2023-01-26

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H03M13/11 ,  H03M13/00

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明申请
    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230067144A1

    公开(公告)日：2023-03-02

    申请号：US17692447

    申请日：2022-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.

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