公开(公告)号：US20190204281A1

公开(公告)日：2019-07-04

申请号：US16109758

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： INHO CHOI ,  Minjin KIM ,  Sungwoo PARK ,  YOUNGDOO JUNG ,  Eunhee JUNG ,  Sungeun JO

IPC: G01N33/00 ,  H01L23/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: G01N33/006 ,  G01N33/0031 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/564 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/3025

Abstract: Disclosed is a gas sensor package. The gas sensor package comprises a package substrate, a controller on the package substrate, a plurality of gas sensors on the controller, and a lid on the package substrate and the lid comprising a hole extending between a first surface and a second surface of the lid, the first surface of the lid facing away the package substrate and the second surface of the lid facing toward the package substrate. The gas sensors sense different types of gases.

公开(公告)号：US20250132234A1

公开(公告)日：2025-04-24

申请号：US18652312

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Yongjae KIM ,  Hyeonjae KIM ,  Sungwoo PARK ,  Junseop BYEON ,  Semin OH

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed are interposers and semiconductor packages. The interposer includes a core layer, an upper wiring layer on the core layer, a plurality of lower pads on a bottom surface of the core layer, a plurality of through vias that vertically penetrate the core layer and electrically connect the upper wiring layer to the lower pads, and a dummy structure on a lower portion of the core layer. The dummy structure includes a dummy layer whose bottom surface is coplanar with the bottom surface of the core layer, a barrier layer between the core layer and the dummy layer, and a dielectric layer between the core layer and the barrier layer. The dummy structure is horizontally spaced apart and electrically insulated from the through vias.

公开(公告)号：US20240112998A1

公开(公告)日：2024-04-04

申请号：US18461569

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjae KIM ,  Sungwoo PARK ,  Seungkwan RYU ,  Yanggyoo JUNG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps, first and second semiconductor devices disposed spaced apart from each other on the interposer and mounted on the interposer via second conductive bumps, and an underfill member filling a space between the first conductive bumps that are between the package substrate and the interposer. The interposer includes a central region and a peripheral region at least partially surrounding the central region. The first conductive bumps include first bump structures disposed on second bonding pads, which are in the central region and on a lower surface of the interposer, respectively, and having a circular shape. The first conductive bumps further include second bump structures disposed on second bonding pads, which are in the peripheral region and on the lower surface of the interposer, respectively, and having an elliptical shape.

公开(公告)号：US20210304482A1

公开(公告)日：2021-09-30

申请号：US17267015

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo PARK ,  Yoonchan CHOI ,  Hyungjoo JIN ,  Sungjun KIM

IPC: G06T13/80 ,  G06F3/0488 ,  G06T11/20 ,  G06T11/00

Abstract: An electronic device according to various embodiments of the present invention includes: a touch screen display; a processor operatively connected to the display; and a memory operatively connected to the processor. The memory may include instructions which, when executed, cause the processor to: display, on the display, a user interface including a first section configured to receive a drawing input and a second section including a plurality of colors and one or more line widths, which are to be selected for the drawing input; execute an animation image file to be displayed on the first section, the animation image file including a procedure of drawing an object with at least one color among the plurality of colors and at least one line width among the one or more line widths; receive, from the display, an input for stopping the execution of the image file; and display a drawing output on the display according to the drawing input, the drawing output including at least one among the color and the line width used when the drawing input is received. Various other embodiments are also possible.

公开(公告)号：US20220350256A1

公开(公告)日：2022-11-03

申请号：US17672937

申请日：2022-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon LEE ,  Maenghyo CHO ,  Changyoung JEONG ,  Muyoung KIM ,  Junghwan MOON ,  Sungwoo PARK ,  Hyungwoo LEE

IPC: G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  G05B19/4099 ,  G06F30/25

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

公开(公告)号：US20220199577A1

公开(公告)日：2022-06-23

申请号：US17478247

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo PARK ,  Ungcheon KIM ,  Heonwoo KIM ,  Yunseok CHOI

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.

公开(公告)号：US20140051243A1

公开(公告)日：2014-02-20

申请号：US14064467

申请日：2013-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-shin YOUN ,  Yonghwan KWON ,  YoungHoon RO ,  Woojae KIM ,  Sungwoo PARK

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Abstract translation: 示例性实施例涉及半导体封装。 半导体封装包括第一衬底，其包括第一焊盘，与第一衬底向上间隔开的第二衬底，并且包括与第一焊盘相对的第二焊盘。 至少一个电极耦合在第一焊盘和第二焊盘之间。 半导体封装包括形成在第一基板和第二基板之间的电极的周边处的引导环。

公开(公告)号：US20240213199A1

公开(公告)日：2024-06-27

申请号：US18227646

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo PARK ,  Yongjae KIM ,  Heonwoo KIM ,  Seung-Kwan RYU

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/13017 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/37001

Abstract: The present disclosure provides semiconductor packages and methods of fabricating the same. In some embodiments, a semiconductor package includes a substrate including first and second regions, a first pad on the first region, a second pad on the second region, a first dielectric layer on the first region and including a first opening exposing the first pad, a second dielectric layer on the second region and including a second opening exposing the second pad, a first bump structure on the first pad and in the first opening, and a second bump structure on the second pad and in the second opening. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. A distance between the substrate and an uppermost end of the first bump structure is longer than a distance between the substrate and an uppermost end of the second bump structure.