公开(公告)号：US20190229011A1

公开(公告)日：2019-07-25

申请号：US16035906

申请日：2018-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Dae SUK ,  Sang Hoon LEE ,  Masuoka SADAAKI ,  Han Su OH

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.

公开(公告)号：US20180175070A1

公开(公告)日：2018-06-21

申请号：US15843139

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Dae SUK ,  Geum Jong BAE ,  Joo Hee JEONG

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L29/10 ,  H01L27/02 ,  H01L23/522 ,  H01L21/84 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/18

CPC classification number: H01L27/1211 ,  H01L21/185 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/7391

Abstract: A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.

公开(公告)号：US20170256608A1

公开(公告)日：2017-09-07

申请号：US15444550

申请日：2017-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Dae SUK ,  Seung Min SONG ,  Geum Jong BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/786

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

公开(公告)号：US20170250291A1

公开(公告)日：2017-08-31

申请号：US15222276

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

公开(公告)号：US20170345946A1

公开(公告)日：2017-11-30

申请号：US15666844

申请日：2017-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.